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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? 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h8s/2268 group, h8s/2264 group hardware manual 16 users manual rev.5.00 2009.09 renesas 16-bit single-chip microcomputer h8s family/h8s/2200 series h8s/2268 hd64f2268 h8s/2266 hd64f2266 h8s/2265 hd64f2265 h8s/2264 hd6432264 hd6432264w h8s/2262 hd6432262 hd6432262w
rev. 5.00 sep. 01, 2009 page ii of l rej09b0071-0500 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials
rev. 5.00 sep. 01, 2009 page iii of l rej09b0071-0500 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products.
rev. 5.00 sep. 01, 2009 page iv of l rej09b0071-0500 configuration of this manual this manual comprises the following items: 1. general precautions in the handling of mpu/mcu products 2. configuration of this manual 3. preface 4. main revisions for this edition the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 5. contents 6. overview 7. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional descrip tion of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. list of registers 9. electrical characteristics 10. appendix 11. index
rev. 5.00 sep. 01, 2009 page v of l rej09b0071-0500 preface this lsi is a high-performance microcontroller (mcu) made up of the h8s/2000 cpu with an internal 32-bit configuration as its core, and the peripheral functions required to configure a system. a single-power flash memory (f-ztat tm ) * version and a masked-rom version are available for this lsi's rom. the f-ztat version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. note: * f-ztat is a trademark of renesas technology corp. target users: this manual was written for us ers who will be using the h8s/2268 group and h8s/2264 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2268 group and h8s/2264 group to the target users. refer to the h8s/2600 series, h8s/2000 series programming manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripher al functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8s/2600 series, h8s/2000 series programming manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 24, list of registers. examples: register name: the following notatio n is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemente d on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right.
rev. 5.00 sep. 01, 2009 page vi of l rej09b0071-0500 number notation: binary is b'xxxx, hexadecimal is h'xxxx, decimal is xxxx signal notation: an overbar is added to a low-active signal: xxxx list of on-chip peripheral functions: group name h8s/2268 group h8s/2264 group product name h8s/2268, h8s/2266, h8s/2265 h8s/2264, h8s/2262 pc break controller (pbc) 2 ? data transfer controller (dtc) 1 ? 16-bit timer pulse unit (tpu) 3 2 8-bit timer (tmr_0 to tmr_3) 4 2 8-bit reload timer (tmr_4) 4 ? watch dog timer (wdt) 2 2 serial communication interface (sci) 3 3 i 2 c bus interface (iic) 2 1 (option) a/d converter 10 10 d/a converter 2 ? lcd controller/driver 40 seg/4 com 40 seg/4 com dtmf generation circuit 1 ? ports 1, 3, 4, 7, 9, f, h, j to n 1, 3, 4, 7, 9, f, h, j to l external interrupts 14 13 interrupt priorities 8 levels ? related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ h8s/2268 group, h8s/2264 group manuals: document title document no. h8s/2268 group, h8s/2264 group hardware manual this manual h8s/2600 series, h8s/2000 series programming manual rej09b0139
rev. 5.00 sep. 01, 2009 page vii of l rej09b0071-0500 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimized linkage editor compiler package ver. 6.01 user's manual rej10b0161 high-performance embedded workshop user's manual rej10j2000 application notes: document title document no. h8s, h8/300 series c/c++ compiler package application note rej05b0464
rev. 5.00 sep. 01, 2009 page viii of l rej09b0071-0500
rev. 5.00 sep. 01, 2009 page ix of l rej09b0071-0500 main revisions for this edition item page revision (see manual for details) 1.4 pin functions table 1.1 pin functions 9 table amended type symbol pin no. i/o function a/d converter, d/a converter * 1 avcc 54 input power supply pin for the a/d converter, d/a converter * 1 and dtmf generation circuit * 1 . if none of the a/d converter, d/a converter * 1 and dtmf generation circuit * 1 is used, connect this pin to the system power supply (vcc level). vref 53 input reference voltage input pin for the a/d converter and d/a converter * 1 . if neither the a/d converter nor d/a converter * 1 is used, connect this pin to the system power supply (vcc level). 2.6 instruction set table 2.1 instruction classification 29 table amended function instructions size types data transfer mov b/w/l 5 pop * 1 , push * 1 w/l ldm * 5 , stm * 5 l movfpe * 3 , movtpe * 3 b note added notes: 5. only register er0 to er6 should be used when using the stm/ldm instruction. 2.6.1 table of instructions classified by function table 2.3 data transfer instructions 31 table amended instruction size * 1 function ldm * 2 l @sp+ rn (register list) pops two or more general registers from the stack. stm * 2 l rn (register list) @?sp pushes two or more general registers onto the stack. note added notes: 2. only register er0 to er6 should be used when using the stm/ldm instruction. 4.8 usage note figure 4.3 operation when sp value is odd 66 figure amended sp h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff r1l pc sp ccr pc sp trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost
rev. 5.00 sep. 01, 2009 page x of l rej09b0071-0500 item page revision (see manual for details) 5.6.5 irq interrupt 102 5.6.5 added 5.6.6 nmi interrupt usage notes 102 5.6.6 added 6.3.4 operation in transitions to power- down modes 107 description deleted ? when the sleep instruction causes a transition from high speed mode to subactive mode (figure 6.2 (b)). 8.2.5 dtc transfer count register a (cra) 119 description amended in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). in repeat mode, crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). in block transfer mode, crah holds the block size while cral functions as an 8-bit block size counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated. 8.5 operation figure 8.5 flowchart of dtc operation 127 figure amended end interupt exception handling * clear dtcer clear an activeation flag note: * for details, see section related to each peripheral module. yes transfer counter = 0 or disel = 1 no 9.1.1 port 1 data direction register (p1ddr) 145 description added p1ddr specifies input or output of the port 1 pins using the individual bits. p1ddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits.
rev. 5.00 sep. 01, 2009 page xi of l rej09b0071-0500 item page revision (see manual for details) 9.2.1 port 3 data direction register (p3ddr) 151 description added p3ddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.2.5 pin functions ? p34/rxd1/sda0 155 description deleted the pin function is switched as shown below according to the combination of the ice bit in iccr_0 of iic_0, re bit in scr of sci_1 and the p34ddr bit. table amended ice 0 1 re 0 1 p34ddr 0 1 pin functions p34 input pin p34 output pin rxd1 input pin sdao i/o pin 9.4.1 port 7 data direction register (p7ddr) 158 description added p7ddr specifies input or output of the port 7 pins using the individual bits. p7ddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.6.1 port f data direction register (pfddr) 163 description added pfddr specifies input or output the port f pins using the individual bits. pfddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits.
rev. 5.00 sep. 01, 2009 page xii of l rej09b0071-0500 item page revision (see manual for details) 9.7.1 port h data direction register (phddr) 165 description added phddr specifies input or output the port h pins using the individual bits. p hddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.8.1 port j data direction register (pjddr) 170 description added pjddr specifies input or output the port j pins using the individual bits. pjddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.9.1 port k data direction register (pkddr) 174 description added pkddr specifies input or output the port k pins using the individual bits. pkddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.10.1 port l data direction register (plddr) 176 description added plddr specifies input or output of the port l pins using the individual bits. plddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits.
rev. 5.00 sep. 01, 2009 page xiii of l rej09b0071-0500 item page revision (see manual for details) 9.11.1 port m data direction register (pmddr) 178 description added pmddr specifies input or output of the port m pins using the individual bits. pmddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.12.1 port n data direction register (pnddr) 181 description added pnddr specifies input or output of the port n pins using the individual bits. p nddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. 9.13 handling of unused pins 183 9.13 added table 9.3 examples of ways to handle unused input pins table added 10.3.1 timer control register (tcr) 192 table amended bit bit name initial value r/w description 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 0 and 1 these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). internal clock edge selection is valid when the input clock is /4 or slower. if the input clock is / 1, this setting is ignored and count at falling edge of is selected. in the h8s/2268 group, if phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. 00: count at rising edge 01: count at falling edge 1x: count at both edges legend: x: don?t care 11.8.1 setting module stop mode 275 11.8.1 added
rev. 5.00 sep. 01, 2009 page xiv of l rej09b0071-0500 item page revision (see manual for details) 12.2.1 timer counter (tcnt) 291 description added tcnt is an 8-bit readable/writable up-counter. tcnt is initialized to h'00 when the tme bit in tcsr is cleared to 0. to initialize tcnt to h?00 while the timer is operating, write h?00 to tcnt directly. see 12.5.7, notes on initializing tcnt by using the tme bit. 12.5.7 notes on initializing tcnt by using the tme bit 302 12.5.7 added 13.3.7 serial status register (ssr) 320 table amended bit bit name initial value r/w description 2 tend 1 r transmit end indicates that transmission has been ended. [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt request and transfer transmission data to tdr (h8s/2268 group only) 13.3.7 serial status register (ssr) 321 table amended bit bit name initial value r/w description 7 tdre 1 r/(w) * 1 transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt request and writes data to tdr (h8s/2268 group only) 6 rdrf 0 r/(w) * 1 receive data register full indicates that the received data is stored in rdr. [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc * 2 is activated by an rxi interrupt and transferred data from rdr (h8s/2268 group only) the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
rev. 5.00 sep. 01, 2009 page xv of l rej09b0071-0500 item page revision (see manual for details) 13.3.7 serial status register (ssr) 322 table amended bit bit name initial value r/w description 5 orer 0 r/(w) * 1 overrun error indicates that an overrun error occurred during reception, causing abnormal termination. [setting condition] when the next serial reception is completed while rdrf = 1 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing condition] when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4 ers 0 r/(w) * 1 error signal status indicates that the status of an error, signal 1 returned from the reception side at reception [setting condition] when the low level of the error signal is sampled [clearing condition] when 0 is written to ers after reading ers = 1 the ers flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 323 table amended bit bit name initial value r/w description 3 per 0 r/(w) * 1 parity error indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [setting condition] when a parity error is detected during reception if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing condition] when 0 is written to per after reading per = 1 the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0.
rev. 5.00 sep. 01, 2009 page xvi of l rej09b0071-0500 item page revision (see manual for details) 13.3.7 serial status register (ssr) 324 table amended bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to tdr. [setting conditions] ? when the te bit in scr is 0 and the ers bit is also 0 ? when the ers bit is 0 and the tdre bit is 1 after the specified interval following transmission of 1-byte data. the timing of bit setting differs according to the register setting as follows: when gm = 0 and blk = 0, 12.5 etu after transmission starts when gm = 0 and blk = 1, 11.5 etu after transmission starts when gm = 1 and blk = 0, 11.0 etu after transmission starts when gm = 1 and blk = 1, 11.0 etu after transmission starts [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt and transfers transmission data to tdr (h8s/2268 group only) note added notes: 2. this bit is cleared by dtc only when disel = 0 with the transfer counter other than 0. 14.4.6 slave transmit operation 423 description added 1. initialize slave receive mode and wait for slave address reception. when making initial settings for slave receive mode, set the acke bit in iccr to 1. this is necessary in order to enable reception of the acknowledge bit after entering slave transmit mode. description amended 4. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. this acknowledge signal is stored in the ackb bit in icsr if the acke bit in has been set to 1, so the ackb bit can be used to determine whether the transfer operation was performed successfully.
rev. 5.00 sep. 01, 2009 page xvii of l rej09b0071-0500 item page revision (see manual for details) 14.4.6 slave transmit operation 424 description added 10. when the stop condition is detected, that is, when sda is changed from low to high when scl is high, the bbsy flag in iccr is cleared to 0 and the stop flag in icsr is set to 1. at the same time, the iric flag is set to 1. if the iric flag has been set, it is cleared to 0. to restart slave transmit mode operation, make the initial settings once again. 15.2 input/output pins table 15.1 pin configuration 445 table amended pin name symbol i/o function analog input pin 0 an0 * input analog input pin 1 an1 * input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input pins note added note: * an0 and an1 can be used only when vcc = avcc. 15.8.4 range of analog power supply and other pin settings 460 description added ? relationship between avcc, avss and vcc, vss. set avss = vss as the relationship between avcc, avss and vcc, vss. if the a/d converter is not used, the avcc and avss pins must not be left open. in addition, analog input pins an0 and an1 can be used only when vcc = avcc. 20.6.1 boot mode table 20.4 boot mode operation 520 table replaced 25.2.2 dc characteristics table 25.2 dc characteristics (1) 600 table amended item symbol min. typ. max. unit test conditions input high voltage res , stby , nmi, fwe, md2, md1 v ih v cc 0. 9 v cc + 0.3 v extal, ports 1, 3, 7, f, j to n, ph0 to ph3 v cc 0.8 v cc + 0.3 v ports 4 * 4 , 9 , ph7 v cc 0.8 av cc + 0.3 * 4 v note added notes: 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v.
rev. 5.00 sep. 01, 2009 page xviii of l rej09b0071-0500 item page revision (see manual for details) 25.2.2 dc characteristics table 25.2 dc characteristics (2) 602 table amended item symbol min. typ. max. unit test conditions input high voltage res , stby ,nmi, fwe, md2, md1 v ih v cc 0. 9 v cc + 0.3 v extal, ports 1, 3, 7, f, j to n, ph0 to ph3 v cc 0.8 v cc + 0.3 v ports 4 * 4 , 9 , ph7 v cc 0.8 v cc + 0.3 * 4 v 603 note added notes: 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v. 25.2.4 a/d conversion characteristics table 25.9 a/d conversion characteristics 615 table condition amended condition a (f-ztat version): v cc = 3.0 v to 5.5 v * , av cc = 2.7 v to 5.5 v * , v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v * , av cc = 4.0 v to 5.5 v * , v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) note added note: * an0 and an1 can be used only when vcc = avcc. 25.3.2 dc characteristics table 25.15 dc characteristics (1) 622 table amended item symbol min. typ. ma x. unit test conditions input high voltage r e s , s t by , nmi, fwe, md2, md1 v ih v cc 0. 9 v cc + 0.3 v extal, ports 1, 3, 7, f, h, j to l v cc 0.8 v cc + 0.3 v ports 4 * 4 , 9 v cc 0.8 av cc + 0.3 * 4 v 623 note added notes: 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v. 25.3.2 dc characteristics table 25.15 dc characteristics (2) 624 table amended item symbol min. typ. ma x. unit test conditions input high voltage r e s , s t by , nmi, fwe, md2, md1 v ih v cc 0. 9 v cc + 0.3 v extal, ports 1, 3, 7, f, h, j to l v cc 0.8 v cc + 0.3 v ports 4 * 4 , 9 v cc 0.8 av cc + 0.3 * 4 v 625 note added notes: 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v.
rev. 5.00 sep. 01, 2009 page xix of l rej09b0071-0500 item page revision (see manual for details) 25.3.4 a/d conversion characteristics table 25.22 a/d conversion characteristics 636 table condition amended condition b (masked-rom version): v cc = 2.7 v to 5.5 v * , av cc = 2.7 v to 5.5 v * , v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) condition d (masked-rom version): v cc = 4.0 v to 5.5 v * , av cc = 4.0 v to 5.5 v * , v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ? 40c to +85c (wide-range specifications) note added note: * an0 and an1 can be used only when vcc = avcc. appendix b product codes 646 to 649packages amended (before) fp-100b (after) fp-100b, fp-100bv (before) tfp-100b (after) tfp-100b, tfp-100bv (before) tfp-100g (after) tfp-100g, tfp-100gv
rev. 5.00 sep. 01, 2009 page xx of l rej09b0071-0500 all trademarks and registered trademarks are the property of their respective owners.
rev. 5.00 sep. 01, 2009 page xxi of l rej09b0071-0500 contents section 1 overview...............................................................................................1 1.1 features ....................................................................................................................... ..........1 1.2 internal block diagram......................................................................................................... 3 1.3 pin arrangement ................................................................................................................ ...5 1.4 pin functions .................................................................................................................. ......7 section 2 cpu..................................................................................................... 13 2.1 features ....................................................................................................................... ........13 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu ....................................14 2.1.2 differences from h8/300 cpu ..............................................................................15 2.1.3 differences from h8/300h cpu............................................................................15 2.2 cpu operating modes ........................................................................................................16 2.2.1 normal mode.........................................................................................................16 2.2.2 advanced mode.....................................................................................................18 2.3 address space.................................................................................................................. ...20 2.4 register configuration........................................................................................................2 1 2.4.1 general registers ...................................................................................................22 2.4.2 program counter (pc) ...........................................................................................23 2.4.3 extended control register (e xr) (h8s/2268 gr oup only)..................................23 2.4.4 condition-code register (ccr) ............................................................................24 2.4.5 initial values of cpu registers .............................................................................25 2.5 data formats................................................................................................................... ....26 2.5.1 general register data formats ..............................................................................26 2.5.2 memory data formats ...........................................................................................28 2.6 instruction set ................................................................................................................ .....29 2.6.1 table of instructions classified by function .........................................................30 2.6.2 basic instruction formats ......................................................................................39 2.7 addressing modes and effective address calculation .......................................................40 2.7.1 register direct ? rn...............................................................................................41 2.7.2 register indirect ? @ern ......................................................................................41 2.7.3 register indirect with displacement ? @(d:16, ern) or @(d:32, ern)................41 2.7.4 register indirect with post -increment or pre-decrement ? @ern+ or @-ern ....42 2.7.5 absolute address ? @aa:8, @aa:16, @aa:24, or @aa:32......................................42 2.7.6 immediate ? #xx:8, #xx:16, or #xx: 32 ...................................................................43 2.7.7 program-counter relative ? @(d:8, pc) or @(d:16, pc)......................................43 2.7.8 memory indirect ? @@aa:8 ..................................................................................43 2.7.9 effective address calculation ...............................................................................44 2.8 processing states.............................................................................................................. ...47
rev. 5.00 sep. 01, 2009 page xxii of l rej09b0071-0500 2.9 usage notes .................................................................................................................... ....49 2.9.1 tas instruction......................................................................................................49 2.9.2 stm/ldm instruction ...........................................................................................49 2.9.3 bit manipulation instructions ................................................................................49 2.9.4 access method for registers with write-only bits...............................................51 section 3 mcu operating modes ...................................................................... 55 3.1 operating mode selection ..................................................................................................55 3.2 register description........................................................................................................... .56 3.2.1 mode control register (mdcr) ...........................................................................56 3.3 operating mode ................................................................................................................. .56 3.4 address map .................................................................................................................... ...57 section 4 exception handling ............................................................................ 59 4.1 exception handling types and priority ..............................................................................59 4.2 exception sources and exception vector table .................................................................60 4.3 reset.......................................................................................................................... ..........61 4.3.1 reset exception handling......................................................................................61 4.3.2 interrupts after reset..............................................................................................62 4.3.3 state of on-chip peripheral modules after reset release.....................................62 4.4 traces (supported only by the h8s/2268 group)..............................................................63 4.5 interrupts ..................................................................................................................... ........63 4.6 trap instruction............................................................................................................... ....64 4.7 stack status after exception handling................................................................................65 4.8 usage note..................................................................................................................... .....65 section 5 interrupt controller............................................................................. 67 5.1 features ....................................................................................................................... ........67 5.2 input/output pins .............................................................................................................. ..70 5.3 register descriptions .......................................................................................................... 71 5.3.1 system control register (syscr) ........................................................................71 5.3.2 interrupt priority registers a to g, i to m, and o (ipra to iprg, ipri to iprm, ipro) (h8s/ 2268 group on ly) .................................................................73 5.3.3 irq enable register (ier) ....................................................................................74 5.3.4 irq sense control registers h and l (iscrh and iscrl) .................................75 5.3.5 irq status register (isr)......................................................................................77 5.3.6 wakeup interrupt request register (iwpr)..........................................................80 5.3.7 interrupt enable register 1 (ienr1) .....................................................................80 5.4 interrupt sources.............................................................................................................. ...81 5.4.1 external interrupts .................................................................................................81 5.4.2 internal interrupts...................................................................................................84
rev. 5.00 sep. 01, 2009 page xxiii of l rej09b0071-0500 5.4.3 interrupt exception handling vector table...........................................................84 5.5 operation...................................................................................................................... .......88 5.5.1 interrupt control modes and interrupt operation ..................................................88 5.5.2 interrupt control mode 0 .......................................................................................92 5.5.3 interrupt control mode 2 (h8s/2268 gro up only) ...............................................94 5.5.4 interrupt exception handling sequence ................................................................95 5.5.5 interrupt res ponse times ......................................................................................97 5.5.6 dtc activation by interrupt (h8s/2268 gr oup only)..........................................98 5.6 usage notes .................................................................................................................... .. 100 5.6.1 contention between interrupt generation and disabling..................................... 100 5.6.2 instructions that di sable interrupts ...................................................................... 101 5.6.3 when interrupts are disabled ............................................................................. 101 5.6.4 interrupts during execution of eepmov instruction.......................................... 102 5.6.5 irq interrupt........................................................................................................ 102 5.6.6 nmi interrupt usage notes.................................................................................. 102 section 6 pc break controller (pbc) ...............................................................103 6.1 features ....................................................................................................................... ...... 103 6.2 register descriptions ........................................................................................................ 10 4 6.2.1 break address register a (bara) ..................................................................... 104 6.2.2 break address register b (barb)...................................................................... 105 6.2.3 break control register a (bcra) ...................................................................... 105 6.2.4 break control register b (bcrb)....................................................................... 106 6.3 operation...................................................................................................................... ..... 106 6.3.1 pc break interrupt due to instruction fetch ....................................................... 106 6.3.2 pc break interrupt due to data access............................................................... 107 6.3.3 notes on pc break interrupt handling ................................................................ 107 6.3.4 operation in transitions to power-down modes ................................................ 107 6.3.5 when instruction execution is delayed by one state ......................................... 108 6.4 usage notes .................................................................................................................... .. 109 6.4.1 module stop mode setting .................................................................................. 109 6.4.2 pc break interrupts.............................................................................................. 109 6.4.3 cmfa and cmfb ............................................................................................... 109 6.4.4 pc break interrupt when dtc is bus master...................................................... 109 6.4.5 pc break set for instruction fetch at address following bsr, jsr, jmp, trapa, rte, or rts instruction ....................................................................... 109 6.4.6 i bit set by ldc, andc, orc, or xorc instruction ....................................... 110 6.4.7 pc break set for instruction fetch at address following bcc instruction.......... 110 6.4.8 pc break set for instruction fetch at branch destination address of bcc instruction..................................................................................................... 110
rev. 5.00 sep. 01, 2009 page xxiv of l rej09b0071-0500 section 7 bus controller....................................................................................111 7.1 basic timing................................................................................................................... .. 111 7.1.1 on-chip memory access timing (rom, ram) ................................................ 111 7.1.2 on-chip peripheral module access ti ming (h'fffdac to h'ffffb f) ........... 112 7.1.3 on-chip peripheral module access timing (h'fffc30 to h'fffca3)............. 112 7.2 bus arbitration (h8s /2268 group only).......................................................................... 113 7.2.1 order of priority of the bus masters.................................................................... 113 7.2.2 bus transfer timing ............................................................................................ 114 7.2.3 resets and the bus controller.............................................................................. 114 section 8 data transfer controller (dtc) ........................................................115 8.1 features ....................................................................................................................... ...... 115 8.2 register descriptions ........................................................................................................ 11 6 8.2.1 dtc mode register a (mra) ............................................................................ 117 8.2.2 dtc mode register b (mrb)............................................................................. 118 8.2.3 dtc source address register (sar).................................................................. 119 8.2.4 dtc destination address register (dar).......................................................... 119 8.2.5 dtc transfer count register a (cra) .............................................................. 119 8.2.6 dtc transfer count re gister b (crb)............................................................... 119 8.2.7 dtc enable register (dtcer) .......................................................................... 120 8.2.8 dtc vector register (dtvecr)........................................................................ 121 8.3 activation sources ............................................................................................................ 1 22 8.4 location of register informa tion and dtc vector table ................................................ 123 8.5 operation...................................................................................................................... ..... 126 8.5.1 normal mode....................................................................................................... 127 8.5.2 repeat mode ........................................................................................................ 128 8.5.3 block transfer mode ........................................................................................... 129 8.5.4 chain transfer ..................................................................................................... 131 8.5.5 interrupts.............................................................................................................. 132 8.5.6 operation timing................................................................................................. 132 8.5.7 number of dtc execution states ....................................................................... 134 8.6 procedures for using dtc................................................................................................ 135 8.6.1 activation by interrupt......................................................................................... 135 8.6.2 activation by software ........................................................................................ 135 8.7 examples of use of dtc .................................................................................................. 136 8.7.1 normal mode....................................................................................................... 136 8.7.2 software activation ............................................................................................. 136 8.8 usage notes .................................................................................................................... .. 137 8.8.1 module stop mode setting .................................................................................. 137 8.8.2 on-chip ram ..................................................................................................... 137 8.8.3 dtce bit setting................................................................................................. 137
rev. 5.00 sep. 01, 2009 page xxv of l rej09b0071-0500 section 9 i/o ports .............................................................................................139 9.1 port 1......................................................................................................................... ........ 145 9.1.1 port 1 data direction register (p1ddr)............................................................. 145 9.1.2 port 1 data register (p1dr)................................................................................ 146 9.1.3 port 1 register (port1)...................................................................................... 146 9.1.4 pin functions ....................................................................................................... 147 9.2 port 3......................................................................................................................... ........ 151 9.2.1 port 3 data direction register (p3ddr)............................................................. 151 9.2.2 port 3 data register (p3dr)................................................................................ 152 9.2.3 port 3 register (port3)...................................................................................... 153 9.2.4 port 3 open drain control register (p3odr)..................................................... 153 9.2.5 pin functions ....................................................................................................... 154 9.3 port 4......................................................................................................................... ........ 157 9.3.1 port 4 register (port4)...................................................................................... 157 9.3.2 pin functions ....................................................................................................... 157 9.4 port 7......................................................................................................................... ........ 157 9.4.1 port 7 data direction register (p7ddr)............................................................. 158 9.4.2 port 7 data register (p7dr)................................................................................ 158 9.4.3 port 7 register (port7)...................................................................................... 159 9.4.4 pin functions ....................................................................................................... 159 9.5 port 9......................................................................................................................... ........ 162 9.5.1 port 9 register (port9)...................................................................................... 162 9.5.2 pin functions ....................................................................................................... 162 9.6 port f......................................................................................................................... ........ 162 9.6.1 port f data direction register (pfddr) ............................................................ 163 9.6.2 port f data regi ster (pfdr) ............................................................................... 163 9.6.3 port f register (portf) ..................................................................................... 164 9.6.4 pin functions ....................................................................................................... 164 9.7 port h......................................................................................................................... ....... 165 9.7.1 port h data directi on register (phddr) ........................................................... 165 9.7.2 port h data register (phdr).............................................................................. 166 9.7.3 port h register (porth) .................................................................................... 166 9.7.4 pin functions ....................................................................................................... 166 9.8 port j ......................................................................................................................... ........ 169 9.8.1 port j data direction register (pjddr).............................................................. 170 9.8.2 port j data register (pjdr)................................................................................. 170 9.8.3 port j register (portj)....................................................................................... 171 9.8.4 port j pull-up mos control register (pjpcr)................................................... 171 9.8.5 wakeup control register (wpcr)...................................................................... 172 9.8.6 pin functions ....................................................................................................... 172 9.8.7 input pull-up mo s function............................................................................... 173
rev. 5.00 sep. 01, 2009 page xxvi of l rej09b0071-0500 9.9 port k......................................................................................................................... ....... 173 9.9.1 port k data directi on register (pkddr) ........................................................... 174 9.9.2 port k data register (pkdr).............................................................................. 174 9.9.3 port k register (portk) .................................................................................... 175 9.9.4 pin functions ....................................................................................................... 175 9.10 port l ......................................................................................................................... ....... 176 9.10.1 port l data direction register (plddr) ............................................................ 176 9.10.2 port l data register (pldr)............................................................................... 177 9.10.3 port l register (portl)..................................................................................... 177 9.10.4 pin functions ....................................................................................................... 178 9.11 port m (h8s/2268 group only) ....................................................................................... 178 9.11.1 port m data direction register (pmddr).......................................................... 178 9.11.2 port m data register (pmdr)............................................................................. 179 9.11.3 port m register (portm)................................................................................... 180 9.11.4 pin functions ....................................................................................................... 180 9.12 port n (h8s/2268 group only) ........................................................................................ 181 9.12.1 port n data directi on register (pnddr) ........................................................... 181 9.12.2 port n data register (pndr).............................................................................. 182 9.12.3 port n register (portn) .................................................................................... 182 9.12.4 pin functions ....................................................................................................... 183 9.13 handling of unused pins .................................................................................................. 183 section 10 16-bit timer pulse unit (tpu) .......................................................185 10.1 features ....................................................................................................................... ...... 185 10.2 input/output pins .............................................................................................................. 190 10.3 register descriptions ........................................................................................................ 19 1 10.3.1 timer control register (tcr)............................................................................. 192 10.3.2 timer mode register (tmdr) ............................................................................ 195 10.3.3 timer i/o control register (tior) ..................................................................... 197 10.3.4 timer interrupt enable register (tier) .............................................................. 207 10.3.5 timer status register (tsr)................................................................................ 209 10.3.6 timer counter (tcnt)........................................................................................ 213 10.3.7 timer general register (tgr) ............................................................................ 213 10.3.8 timer start register (tstr)................................................................................ 214 10.3.9 timer synchro register (tsyr) ......................................................................... 215 10.4 interface to bus master ..................................................................................................... 216 10.4.1 16-bit registers ................................................................................................... 216 10.4.2 8-bit registers ..................................................................................................... 216 10.5 operation...................................................................................................................... ..... 218 10.5.1 basic functions.................................................................................................... 218 10.5.2 synchronous op eration........................................................................................ 223
rev. 5.00 sep. 01, 2009 page xxvii of l rej09b0071-0500 10.5.3 buffer operation (h8s /2268 group only) .......................................................... 225 10.5.4 pwm modes ........................................................................................................ 228 10.5.5 phase counting mode (h 8s/2268 group only) .................................................. 233 10.6 interrupt sources.............................................................................................................. . 238 10.7 dtc activation (h8s /2268 group on ly)......................................................................... 239 10.8 a/d converter activation................................................................................................. 239 10.9 operation timing.............................................................................................................. 2 40 10.9.1 input/output timing ............................................................................................ 240 10.9.2 interrupt signal timing........................................................................................ 244 10.10 usage notes .................................................................................................................... .. 247 10.10.1 module stop mode setting .................................................................................. 247 10.10.2 input clock re strictions ...................................................................................... 247 10.10.3 caution on period setting .................................................................................... 248 10.10.4 contention between tcnt write and clear operations..................................... 248 10.10.5 contention between tcnt write and increment operations.............................. 249 10.10.6 contention between tgr write and compare match ......................................... 250 10.10.7 contention between buffer register write and compare match (h8s/2268 group only) ...................................................................................... 251 10.10.8 contention between tgr read and input capture.............................................. 252 10.10.9 contention between tgr write and input capture............................................. 253 10.10.10 contention between buffer register write and input capture (h8s/2268 group only)..................................................................................... 254 10.10.11 contention between overflow/underflow and counter clearing ...................... 255 10.10.12 contention between tcnt write and overflow/underflow ............................. 256 10.10.13 multiplexing of i/o pins .................................................................................... 256 10.10.14 interrupts in modul e stop mode ........................................................................ 256 section 11 8-bit timers .....................................................................................257 11.1 8-bit timer module (tmr_0, tm r_1, tmr_2, and tmr_3)........................................ 257 11.1.1 features................................................................................................................ 257 11.2 input/output pins .............................................................................................................. 259 11.3 register descriptions ........................................................................................................ 25 9 11.3.1 timer counter (tcnt)........................................................................................ 260 11.3.2 time constant register a (tcora)................................................................... 260 11.3.3 time constant register b (tcorb) ................................................................... 260 11.3.4 timer control register (tcr)............................................................................. 261 11.3.5 timer control/status register (tcsr)................................................................ 263 11.4 operation...................................................................................................................... ..... 268 11.4.1 pulse output......................................................................................................... 268 11.5 operation timing.............................................................................................................. 2 69 11.5.1 tcnt incrementation timing ............................................................................. 269
rev. 5.00 sep. 01, 2009 page xxviii of l rej09b0071-0500 11.5.2 timing of cmfa and cmfb setting when a compare-match occurs.............. 270 11.5.3 timing of timer output when a compare-match occurs .................................. 270 11.5.4 timing of compare-match clear when a compare-match occurs .................... 271 11.5.5 tcnt external reset timing .............................................................................. 271 11.5.6 timing of overflow fl ag (ovf) setting ............................................................. 272 11.6 operation with cascaded connection ............................................................................... 273 11.6.1 16-bit count mode .............................................................................................. 273 11.6.2 compare-match count m ode .............................................................................. 273 11.7 interrupt sources.............................................................................................................. . 274 11.7.1 interrupt sources and dtc activation ................................................................ 274 11.7.2 a/d converter activation.................................................................................... 274 11.8 usage notes .................................................................................................................... .. 275 11.8.1 setting module stop mo de .................................................................................. 275 11.8.2 contention between tcnt write and clear........................................................ 275 11.8.3 contention between tcnt write and increment ................................................ 276 11.8.4 contention between tcor write and compare-match ...................................... 277 11.8.5 contention between compare-matches a and b................................................. 277 11.8.6 switching of internal clocks and tcnt operation............................................. 278 11.8.7 contention between interrup ts and module stop mode ...................................... 279 11.9 8-bit reload timer (tmr_4) (h8s/2268 group only) ................................................... 280 11.9.1 features................................................................................................................ 280 11.9.2 input/output pins ................................................................................................. 281 11.10 register descriptions ........................................................................................................ 28 2 11.10.1 timer control registers 4 to 7 (tcr_4 to tcr_7)............................................. 282 11.10.2 timer counters 4 to 7 (tcnt4 to tcnt7)......................................................... 283 11.10.3 time reload registers 4 to 7 (tlr_4 to tlr_7) ............................................... 283 11.11 operation...................................................................................................................... ..... 284 11.11.1 interval timer operation ..................................................................................... 284 11.11.2 automatic reload timer operation..................................................................... 285 11.11.3 cascaded connection........................................................................................... 285 11.12 usage notes .................................................................................................................... .. 287 11.12.1 conflict between write to tlr and count up/automatic reload ...................... 287 11.12.2 switchover of internal cloc k and tcnt operation ............................................ 287 11.12.3 interrupt during module stop .............................................................................. 287 section 12 watchdog timer (wdt) .................................................................289 12.1 features ....................................................................................................................... ...... 289 12.2 register descriptions ........................................................................................................ 29 1 12.2.1 timer counter (tcnt)........................................................................................ 291 12.2.2 timer control/status register (tcsr)................................................................ 291 12.2.3 reset control/status register (rstcsr) (only wdt_0) .................................. 295
rev. 5.00 sep. 01, 2009 page xxix of l rej09b0071-0500 12.3 operation...................................................................................................................... ..... 296 12.3.1 watchdog time r mode ........................................................................................ 296 12.3.2 interval timer mode ............................................................................................ 297 12.3.3 timing of setting overfl ow flag (ovf) ............................................................. 298 12.3.4 timing of setting watchdog time r overflow flag (wovf) ............................. 298 12.4 interrupt sources.............................................................................................................. . 299 12.5 usage notes .................................................................................................................... .. 299 12.5.1 notes on register access..................................................................................... 299 12.5.2 contention between timer counter (tcnt) write and increment ..................... 301 12.5.3 changing value of cks2 to cks0...................................................................... 301 12.5.4 switching between watchdog timer mode and interval timer mode................ 301 12.5.5 internal reset in watchdog time r mode............................................................. 302 12.5.6 ovf flag clearing in interval timer mode ........................................................ 302 12.5.7 notes on initializing tcnt by using the tme bit............................................. 302 section 13 serial communication interface (sci) ............................................303 13.1 features ....................................................................................................................... ...... 303 13.2 input/output pins .............................................................................................................. 307 13.3 register descriptions ........................................................................................................ 30 7 13.3.1 receive shift register (rsr) .............................................................................. 308 13.3.2 receive data register (rdr) .............................................................................. 308 13.3.3 transmit data register (tdr)............................................................................. 308 13.3.4 transmit shift register (tsr) ............................................................................. 309 13.3.5 serial mode register (smr)................................................................................ 309 13.3.6 serial control re gister (scr).............................................................................. 313 13.3.7 serial status register (ssr) ................................................................................ 318 13.3.8 smart card mode register (scmr) .................................................................... 325 13.3.9 bit rate register (brr) ...................................................................................... 326 13.3.10 serial expansion mode register (semr_0) ....................................................... 334 13.4 operation in async hronous mode .................................................................................... 338 13.4.1 data transfer format........................................................................................... 338 13.4.2 receive data sampling timing and reception margin in asynchronous mode .................................................................................................................... 340 13.4.3 clock.................................................................................................................... 341 13.4.4 sci initialization (as ynchronous mode) ............................................................. 342 13.4.5 serial data transmission (asynchronous mode) ................................................ 343 13.4.6 serial data reception (a synchronous mode)...................................................... 345 13.5 multiprocessor communication function......................................................................... 349 13.5.1 multiprocessor serial da ta transmission ............................................................ 351 13.5.2 multiprocessor serial data reception ................................................................. 352 13.6 operation in clocked synchronous mode ........................................................................ 355
rev. 5.00 sep. 01, 2009 page xxx of l rej09b0071-0500 13.6.1 clock.................................................................................................................... 355 13.6.2 sci initialization (clocked synchronous mode) ................................................. 355 13.6.3 serial data transmission (clo cked synchron ous mode ) .................................... 356 13.6.4 serial data reception (clock ed synchronous mode).......................................... 359 13.6.5 simultaneous serial data transmissi on and reception (clocked synchronous mode)................................................................................................................... 361 13.7 operation in smart card interface .................................................................................... 363 13.7.1 pin connection example...................................................................................... 363 13.7.2 data format (except for block transfer mode).................................................. 363 13.7.3 block transfer mode ........................................................................................... 365 13.7.4 receive data sampling timi ng and reception margin....................................... 366 13.7.5 initialization ......................................................................................................... 367 13.7.6 serial data transmission (except for block transfer mode).............................. 367 13.7.7 serial data reception (except for block transfer mode) ................................... 371 13.7.8 clock output control........................................................................................... 372 13.8 interrupt sources.............................................................................................................. . 374 13.8.1 interrupts in normal serial communication interface mode............................... 374 13.8.2 interrupts in smart card interface mode ............................................................. 375 13.9 usage notes .................................................................................................................... .. 376 13.9.1 module stop mode setting .................................................................................. 376 13.9.2 break detection and processing (asynchronous mode only)............................. 376 13.9.3 mark state and break detection (asynchronous mode only) ............................ 376 13.9.4 receive error flags and transmit op erations (clocked synchronous mode only).......................................................................................................... 377 13.9.5 restrictions on use of dt c (h8s/2268 gr oup only) ......................................... 377 13.9.6 operation in case of mode transition................................................................. 378 13.9.7 switching from sck pin function to port pin function: .................................... 381 13.9.8 assignment and selection of registers................................................................ 382 section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) ...............................383 14.1 features ....................................................................................................................... ...... 383 14.2 input/output pins .............................................................................................................. 386 14.3 register descriptions ........................................................................................................ 38 7 14.3.1 i 2 c bus data register (icdr) ............................................................................. 388 14.3.2 slave address register (sar) ............................................................................. 390 14.3.3 second slave address register (sarx) ............................................................. 390 14.3.4 i 2 c bus mode register (icmr)........................................................................... 391 14.3.5 serial control regi ster x (scrx)....................................................................... 394 14.3.6 i 2 c bus control register (iccr) ......................................................................... 395 14.3.7 i 2 c bus status register (icsr)............................................................................ 401
rev. 5.00 sep. 01, 2009 page xxxi of l rej09b0071-0500 14.3.8 ddc switch register (ddcswr) ...................................................................... 405 14.4 operation...................................................................................................................... ..... 406 14.4.1 i 2 c bus data format ............................................................................................ 406 14.4.2 initial se tting........................................................................................................ 408 14.4.3 master transmit operation .................................................................................. 408 14.4.4 master receive operation.................................................................................... 412 14.4.5 slave receive operation...................................................................................... 417 14.4.6 slave transmit operation .................................................................................... 422 14.4.7 iric setting timing and scl control ................................................................ 425 14.4.8 operation using the dtc (h8s/2268 gro up only) ............................................ 426 14.4.9 noise canceler ..................................................................................................... 427 14.4.10 initialization of in ternal state .............................................................................. 427 14.5 interrupt source ............................................................................................................... . 429 14.6 usage notes .................................................................................................................... .. 429 section 15 a/d converter..................................................................................443 15.1 features ....................................................................................................................... ...... 443 15.2 input/output pins .............................................................................................................. 445 15.3 register descriptions ........................................................................................................ 44 6 15.3.1 a/d data registers a to d (addra to addrd) ............................................. 446 15.3.2 a/d control/status register (adcsr) ............................................................... 447 15.3.3 a/d control register (adcr) ............................................................................ 449 15.4 interface to bus master ..................................................................................................... 450 15.5 operation...................................................................................................................... ..... 451 15.5.1 single mode......................................................................................................... 451 15.5.2 scan mode ........................................................................................................... 453 15.5.3 input sampling and a/ d conversi on time.......................................................... 454 15.5.4 external trigger input ti ming............................................................................. 456 15.6 interrupt source ............................................................................................................... . 456 15.7 a/d conversion accuracy definitions ............................................................................. 457 15.8 usage notes .................................................................................................................... .. 459 15.8.1 module stop mode setting .................................................................................. 459 15.8.2 permissible signal s ource impedance ................................................................. 459 15.8.3 influences on absolute accuracy ........................................................................ 459 15.8.4 range of analog power supp ly and other pin settings ...................................... 460 15.8.5 notes on board design ........................................................................................ 460 15.8.6 notes on noise c ountermeasures ........................................................................ 460 section 16 d/a converter..................................................................................463 16.1 features ....................................................................................................................... ...... 463 16.2 input/output pins .............................................................................................................. 464
rev. 5.00 sep. 01, 2009 page xxxii of l rej09b0071-0500 16.3 register description.......................................................................................................... 4 64 16.3.1 d/a data registers 0 and 1 (dadr0 and dadr1)............................................ 464 16.3.2 d/a control register (dacr) ............................................................................ 465 16.4 operation...................................................................................................................... ..... 466 16.5 usage notes .................................................................................................................... .. 467 16.5.1 analog power supply current in power-down mode......................................... 467 16.5.2 setting for module stop mode............................................................................. 467 section 17 lcd controller/driver ....................................................................469 17.1 features ....................................................................................................................... ...... 469 17.2 input/output pins .............................................................................................................. 471 17.3 register descriptions ........................................................................................................ 47 2 17.3.1 lcd port control register (lpcr)..................................................................... 472 17.3.2 lcd control register (lcr)............................................................................... 476 17.3.3 lcd control register 2 (lcr2).......................................................................... 478 17.4 operation...................................................................................................................... ..... 482 17.4.1 settings up to lcd display ................................................................................. 482 17.4.2 relationship between lc d ram and display .................................................... 483 17.4.3 triple step-up voltage circuit (supported only by the h8s/2268 group)........ 488 17.4.4 operation in power-down modes ....................................................................... 489 17.4.5 low-power lcd drive........................................................................................ 490 17.4.6 boosting the lcd drive power supply............................................................... 492 section 18 dtmf generation circuit ...............................................................493 18.1 features ....................................................................................................................... ...... 493 18.2 input/output pins .............................................................................................................. 494 18.3 register descriptions ........................................................................................................ 49 5 18.3.1 dtmf control register (dtcr)......................................................................... 495 18.3.2 dtmf load register (dtlr)............................................................................. 496 18.4 operation...................................................................................................................... ..... 497 18.4.1 output waveform ................................................................................................ 497 18.4.2 operation flow .................................................................................................... 498 18.5 application circuit example............................................................................................. 499 18.6 usage notes .................................................................................................................... .. 499 section 19 ram ................................................................................................501 section 20 rom ................................................................................................503 20.1 features ....................................................................................................................... ...... 503 20.2 mode transitions .............................................................................................................. 5 04 20.3 block confi guration.......................................................................................................... 50 8
rev. 5.00 sep. 01, 2009 page xxxiii of l rej09b0071-0500 20.4 input/output pins .............................................................................................................. 511 20.5 register descriptions ........................................................................................................ 51 1 20.5.1 flash memory control register 1 (flmcr1)..................................................... 512 20.5.2 flash memory control register 2 (flmcr2)..................................................... 513 20.5.3 erase block regist er 1 (e br1) ........................................................................... 514 20.5.4 erase block regist er 2 (e br2) ........................................................................... 515 20.5.5 ram emulation register (ramer)................................................................... 515 20.5.6 flash memory power control register (flpwcr) ............................................ 516 20.5.7 serial control regi ster x (scrx)....................................................................... 517 20.6 on-board programming modes........................................................................................ 518 20.6.1 boot m ode ........................................................................................................... 518 20.6.2 programming/erasing in user program mode..................................................... 521 20.7 flash memory emulation in ram ................................................................................... 522 20.8 flash memory programming/erasing ............................................................................... 524 20.8.1 program/program-verify ..................................................................................... 525 20.8.2 erase/erase-verify............................................................................................... 527 20.8.3 interrupt handling when progra mming/erasing flash memory.......................... 527 20.9 program/erase protection ................................................................................................. 529 20.9.1 hardware protection ............................................................................................ 529 20.9.2 software protection.............................................................................................. 529 20.9.3 error protection.................................................................................................... 529 20.10 interrupt handling when progra mming/erasing flash memory....................................... 530 20.11 programmer mode ............................................................................................................ 530 20.12 power-down states for flash memory............................................................................. 532 20.13 flash memory programming and erasing precautions ..................................................... 533 20.14 note on switching from f-ztat version to masked rom version .............................. 538 section 21 clock pulse generator .....................................................................539 21.1 register descriptions ........................................................................................................ 54 0 21.1.1 system clock control register (sckcr) ........................................................... 540 21.1.2 low-power control register (lpwrcr) ........................................................... 541 21.2 system clock oscillator.................................................................................................... 543 21.2.1 connecting a crystal resonator........................................................................... 543 21.2.2 external clock input ............................................................................................ 544 21.2.3 notes on switching external clock ..................................................................... 546 21.3 duty adjustment circuit................................................................................................... 547 21.4 medium-speed clock divider .......................................................................................... 547 21.5 bus master clock se lection circuit .................................................................................. 547 21.6 subclock os cillator ........................................................................................................... 5 48 21.6.1 connecting 32.768-khz crystal resonator.......................................................... 548 21.6.2 handling pins when subclock not required........................................................ 549
rev. 5.00 sep. 01, 2009 page xxxiv of l rej09b0071-0500 21.7 subclock waveform generation circuit ........................................................................... 549 21.8 usage notes .................................................................................................................... .. 549 21.8.1 note on crystal resonator ................................................................................... 549 21.8.2 note on board design.......................................................................................... 550 21.8.3 note on using a crystal resonator...................................................................... 550 section 22 power-down modes ........................................................................551 22.1 register description.......................................................................................................... 5 56 22.1.1 standby control regi ster (sbycr) .................................................................... 556 22.1.2 module stop control registers a to d (mstpcra to mstpcrd) .................. 558 22.2 medium-speed mode ........................................................................................................ 560 22.3 sleep mode ..................................................................................................................... .. 561 22.3.1 sleep mode .......................................................................................................... 561 22.3.2 exiting sleep mode.............................................................................................. 561 22.4 software st andby m ode.................................................................................................... 562 22.4.1 software st andby m ode....................................................................................... 562 22.4.2 clearing software standby mode ........................................................................ 562 22.4.3 oscillation settling time after cl earing software standby mode....................... 563 22.4.4 software standby mode ap plication ex ample.................................................... 563 22.5 hardware standby mode .................................................................................................. 564 22.5.1 hardware standby mode ..................................................................................... 564 22.5.2 clearing hardware standby mode....................................................................... 564 22.5.3 hardware standby mode ti ming......................................................................... 565 22.6 module stop mode............................................................................................................ 565 22.7 watch mode..................................................................................................................... . 566 22.7.1 transition to watch mode ................................................................................... 566 22.7.2 exiting watch mode ............................................................................................ 566 22.8 sub-sleep mode................................................................................................................ 5 67 22.8.1 transition to sub-sleep mode ............................................................................. 567 22.8.2 exiting sub-sleep mode ...................................................................................... 567 22.9 sub-active mode .............................................................................................................. 56 8 22.9.1 transition to sub-active mode............................................................................ 568 22.9.2 exiting sub-active mode .................................................................................... 568 22.10 direct transitions............................................................................................................. . 569 22.10.1 direct transitions from high-sp eed mode to sub-active mode ........................ 569 22.10.2 direct transitions from sub-activ e mode to high-speed mode ........................ 569 22.11 usage notes .................................................................................................................... .. 569 22.11.1 i/o port status...................................................................................................... 569 22.11.2 current dissipation during osc illation settling wait period ............................... 569 22.11.3 dtc module stop (supported only by the h8s/2268 group)............................ 569 22.11.4 on-chip peripheral module interrupt.................................................................. 570
rev. 5.00 sep. 01, 2009 page xxxv of l rej09b0071-0500 22.11.5 writing to mstpcr ............................................................................................ 570 22.11.6 entering subactive/watch mode and dtc module stop (supported only by h8s/2268 group) ................................................................ 570 section 23 power supply circuit.......................................................................571 23.1 when internal power step-down circuit is used ............................................................ 571 section 24 list of registers ...............................................................................573 24.1 register addresses ( by function module, in address order) .......................................... 574 24.2 register bits.................................................................................................................. .... 582 24.3 register states in each operating mode........................................................................... 590 section 25 electrical characteristics .................................................................597 25.1 power supply voltage and op erating freque ncy range .................................................. 597 25.2 electrical characteristics of h8s/2268 group .................................................................. 599 25.2.1 absolute maximum ratings ................................................................................ 599 25.2.2 dc characteristics ............................................................................................... 600 25.2.3 ac characteristics ............................................................................................... 610 25.2.4 a/d conversion characteristics........................................................................... 615 25.2.5 d/a conversion characteristics........................................................................... 616 25.2.6 lcd characteristics............................................................................................. 617 25.2.7 dtmf characteristics.......................................................................................... 618 25.2.8 flash memory characteristics ............................................................................. 619 25.3 electrical characteristics of h8s/2264 group .................................................................. 621 25.3.1 absolute maximum ratings ................................................................................ 621 25.3.2 dc characteristics ............................................................................................... 622 25.3.3 ac characteristics ............................................................................................... 631 25.3.4 a/d conversion characteristics........................................................................... 636 25.3.5 lcd characteristics............................................................................................. 637 25.4 operation timing.............................................................................................................. 6 38 25.4.1 oscillator settl ing timing.................................................................................... 638 25.4.2 control signal timings........................................................................................ 638 25.4.3 timing of on-chip pe ripheral m odules .............................................................. 639 25.5 usage note..................................................................................................................... ... 641 appendix a i/o port states in each pin state...................................................643 a.1 i/o port state in each pin state of h8s/2268 group........................................................ 643 a.2 i/o port state in each pin state of h8s/2264 group........................................................ 644 appendix b product codes................................................................................646
rev. 5.00 sep. 01, 2009 page xxxvi of l rej09b0071-0500 appendix c package dimensions .....................................................................650 index .........................................................................................................653
rev. 5.00 sep. 01, 2009 page xxxvii of l rej09b0071-0500 figures section 1 overview figure 1.1 internal block di agram of h8s/2268 group ......................................................... 3 figure 1.2 internal block di agram of h8s/2264 group ......................................................... 4 figure 1.3 pin arrangement of h8s/2268 group.................................................................... 5 figure 1.4 pin arrangement of h8s/2264 group.................................................................... 6 section 2 cpu figure 2.1 exception vector table (normal mode)................................................................ 17 figure 2.2 stack structure in normal mode............................................................................ 17 figure 2.3 exception vector table (advanced mode)............................................................ 18 figure 2.4 stack structure in advanced mode........................................................................ 19 figure 2.5 memory map.......................................................................................................... 20 figure 2.6 cpu registers ....................................................................................................... .21 figure 2.7 usage of general registers .................................................................................... 22 figure 2.8 stack status ........................................................................................................ .... 23 figure 2.9 general register data formats (1)......................................................................... 26 figure 2.9 general register data formats (2)......................................................................... 27 figure 2.10 memory data formats............................................................................................ 28 figure 2.11 instruction formats (examples) ............................................................................. 40 figure 2.12 branch address specifica tion in memory indirect mode...................................... 44 figure 2.13 state transitions.................................................................................................. ... 48 figure 2.14 flowchart of access method for registers with write-only bits.......................... 52 section 3 mcu operating modes figure 3.1 address map (1)..................................................................................................... 57 figure 3.1 address map (2)..................................................................................................... 58 section 4 exception handling figure 4.1 reset sequence (advanced m ode with on-chip rom enabled)........................... 62 figure 4.2 stack status after excep tion handling (advanced mode) ..................................... 65 figure 4.3 operation when sp value is odd........................................................................... 66 section 5 interrupt controller figure 5.1 block diagram of interr upt controller for h8s/2268 group................................. 68 figure 5.2 block diagram of interr upt controller for h8s/2264 group................................. 69 figure 5.3 block diagram of irqn interrupts......................................................................... 81 figure 5.4 set timing for irqnf ............................................................................................ 82 figure 5.5 block diagram of interrupts wkp7 to wkp0 ....................................................... 83
rev. 5.00 sep. 01, 2009 page xxxviii of l rej09b0071-0500 figure 5.6 iwpfn setting timing ........................................................................................... 83 figure 5.7 block diagram of interrupt c ontrol operation for h8s/2268 group .................... 89 figure 5.8 block diagram of interrupt c ontrol operation for h8s/2264 group .................... 90 figure 5.9 flowchart of procedure up to in terrupt acceptance in interrupt control mode 0 ................................................................................................................... 93 figure 5.10 flowchart of procedure up to in terrupt acceptance in control mode 2 ............... 95 figure 5.11 interrupt exception handling................................................................................. 96 figure 5.12 dtc and interrupt controller................................................................................. 99 figure 5.13 contention between interr upt generation and disabling ....................................... 101 section 6 pc break controller (pbc) figure 6.1 block diagram of pc break controller ................................................................. 104 figure 6.2 operation in powe r-down mode transitions ........................................................ 108 section 7 bus controller figure 7.1 on-chip memory access cycle............................................................................. 111 figure 7.2 on-chip peripheral module a ccess cycle (h'fffdac to h'ffff bf) ................ 112 figure 7.3 on-chip peripheral module a ccess cycle (h'fffc30 to h'fffca3) ................. 113 section 8 data transfer controller (dtc) figure 8.1 block diagram of dtc .......................................................................................... 116 figure 8.2 block diagram of dt c activation source control ............................................... 123 figure 8.3 the location of dtc regist er information in address space .............................. 124 figure 8.4 correspondence between dtc vector address and register information ............ 124 figure 8.5 flowchart of dtc operation ................................................................................. 127 figure 8.6 memory mappi ng in normal mode ....................................................................... 128 figure 8.7 memory mapping in repeat mode ........................................................................ 129 figure 8.8 memory mapping in block transf er mode ........................................................... 130 figure 8.9 chain transfer operation....................................................................................... 131 figure 8.10 dtc operation timi ng (example in normal mode or repeat mode) .................. 132 figure 8.11 dtc operation timing (example of block transfer mode, with block size of 2) ................................................................................................................ 133 figure 8.12 dtc operation timing (e xample of chain transfer) ........................................... 133 section 9 i/o ports figure 9.1 types of open drain outputs ................................................................................ 154 section 10 16-bit timer pulse unit (tpu) figure 10.1 block diagram of tpu for h8s/2268 group......................................................... 188 figure 10.2 block diagram of tpu for h8s/2264 group......................................................... 189 figure 10.3 16-bit register access operation [bus master ? tcnt (16 bits) ] ..................... 216
rev. 5.00 sep. 01, 2009 page xxxix of l rej09b0071-0500 figure 10.4 8-bit register access operation [bus master ? tcr (upper 8 bits) ] ................. 216 figure 10.5 8-bit register access operation [bus master ? tmdr (lower 8 bits) ] ............. 217 figure 10.6 8-bit register access operation [bus master ? tcr and tmdr (16 bits) ] ....... 217 figure 10.7 example of counter operation setting procedure ................................................. 218 figure 10.8 free-running co unter operation ........................................................................... 219 figure 10.9 periodic c ounter operation.................................................................................... 220 figure 10.10 example of setting procedure fo r waveform output by compare match............. 220 figure 10.11 example of 0 outp ut/1 output operation .............................................................. 221 figure 10.12 example of toggle output operation .................................................................... 221 figure 10.13 example of input capt ure operation setting procedure ........................................ 222 figure 10.14 example of input capture operation ..................................................................... 222 figure 10.15 example of synchronous operation setting procedure ......................................... 223 figure 10.16 example of s ynchronous op eration....................................................................... 224 figure 10.17 compare match buffer operation.......................................................................... 225 figure 10.18 input captur e buffer operation.............................................................................. 225 figure 10.19 example of buffer operation setting procedure.................................................... 226 figure 10.20 example of bu ffer operation (1) ........................................................................... 227 figure 10.21 example of bu ffer operation (2) ........................................................................... 228 figure 10.22 example of pwm mode setting procedure ........................................................... 230 figure 10.23 example of pwm mode operation (1) .................................................................. 231 figure 10.24 example of pwm mode operation (2) .................................................................. 231 figure 10.25 example of pwm mode operation (3) .................................................................. 232 figure 10.26 example of phase c ounting mode setting procedure............................................ 233 figure 10.27 example of phase counting mode 1 operation ..................................................... 234 figure 10.28 example of phase counting mode 2 operation ..................................................... 235 figure 10.29 example of phase counting mode 3 operation ..................................................... 236 figure 10.30 example of phase counting mode 4 operation ..................................................... 237 figure 10.31 count timing in in ternal clock operation............................................................. 240 figure 10.32 count timing in ex ternal clock operation ........................................................... 240 figure 10.33 output comp are output timing ............................................................................ 241 figure 10.34 input captur e input signa l timing......................................................................... 241 figure 10.35 counter clear timing (compare match) ............................................................... 242 figure 10.36 counter clear timing (input capture) ................................................................... 242 figure 10.37 buffer operation timing (compare match) .......................................................... 243 figure 10.38 buffer operation timing (input capture) .............................................................. 243 figure 10.39 tgi interrupt ti ming (compare match) ................................................................ 244 figure 10.40 tgi interrupt timing (input capture).................................................................... 245 figure 10.41 tciv inte rrupt setting timing............................................................................... 245 figure 10.42 tciu interrupt setting timing (h8s/2268 group only)....................................... 246 figure 10.43 timing for status flag clearing by cpu ............................................................... 246 figure 10.44 timing for status flag clearing by dtc activ ation (h8s/2268 group only)...... 247
rev. 5.00 sep. 01, 2009 page xl of l rej09b0071-0500 figure 10.45 phase difference, overlap, an d pulse width in phase counting mode (h8s/2268 group only)......................................................................................... 248 figure 10.46 contention between tcnt write and clear operations........................................ 249 figure 10.47 contention between tcnt write and increment operations ................................ 249 figure 10.48 contention between tg r write and compare match ........................................... 250 figure 10.49 contention between buffer register write and compare match........................... 251 figure 10.50 contention between tg r read and input capture ................................................ 252 figure 10.51 contention between tg r write and input capture ............................................... 253 figure 10.52 contention between buffer register write and input capture............................... 254 figure 10.53 contention between ov erflow and count er clearing ............................................ 255 figure 10.54 contention between tcnt write and overflow.................................................... 256 section 11 8-bit timers figure 11.1 block diagram of 8-bit timer module.................................................................. 258 figure 11.2 example of pulse output........................................................................................ 268 figure 11.3 count timing for internal cloc k inpu t................................................................... 269 figure 11.4 count timing for external cl ock in put ................................................................. 269 figure 11.5 timing of cmf setting .......................................................................................... 270 figure 11.6 timing of timer output ......................................................................................... 270 figure 11.7 timing of compare-match clear ........................................................................... 271 figure 11.8 timing of clearing by external re set input .......................................................... 271 figure 11.9 timing of ovf setting........................................................................................... 272 figure 11.10 contention between tcnt write and clear .......................................................... 275 figure 11.11 contention between tcnt write and increment................................................... 276 figure 11.12 contention between tc or write and compare-match ........................................ 277 figure 11.13 block diagram of 8-bit reload timer................................................................... 281 figure 11.14 operation in interval timer mode ......................................................................... 284 figure 11.15 operation in automatic reload timer mode......................................................... 285 figure 11.16 channel relationship of cascaded connection...................................................... 286 section 12 watchdog timer (wdt) figure 12.1 block diag ram of wdt_0 ..................................................................................... 290 figure 12.2 block diag ram of wdt_1 ..................................................................................... 290 figure 12.3 watchdog timer mode operation.......................................................................... 297 figure 12.4 interval timer mode operation.............................................................................. 297 figure 12.5 timing of ovf setting........................................................................................... 298 figure 12.6 timing of wovf setting....................................................................................... 298 figure 12.7 writing to tcnt, tcsr (wdt_0) ....................................................................... 299 figure 12.8 writing to rstcsr ............................................................................................... 300 figure 12.9 contention between tcnt write and increment................................................... 301
rev. 5.00 sep. 01, 2009 page xli of l rej09b0071-0500 section 13 serial communication interface (sci) figure 13.1 block diagram of sci_0........................................................................................ 305 figure 13.2 block diagram of sci_1 or sci_2 ........................................................................ 306 figure 13.3 example of internal base clock when average transfer rate is selected (1) ...... 336 figure 13.4 example of internal base clock when average transfer rate is selected (2) ...... 337 figure 13.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) ............................................................................................ 338 figure 13.6 receive data sampling timing in asynchr onous m ode ....................................... 340 figure 13.7 relationship between output clock and transfer data phase (asynchronous mode)............................................................................................ 341 figure 13.8 sample sci in itialization flowchart ...................................................................... 342 figure 13.9 example of operation in transmission in asynchronous mode (example with 8-bit data, pa rity, one stop bit) ................................................................... 343 figure 13.10 sample serial transmission flowchart .................................................................. 344 figure 13.11 example of sci operation in r eception (example with 8-bit data, parity, one stop bit).......................................................................................................... 345 figure 13.12 sample serial r eception data flowchart (1) ......................................................... 347 figure 13.12 sample serial r eception data flowchart (2) ......................................................... 348 figure 13.13 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) ....................................................................... 350 figure 13.14 sample multiprocessor se rial transmissi on flowchart ......................................... 351 figure 13.15 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit).......................................................................... 352 figure 13.16 sample multiprocessor se rial reception flowchart (1)......................................... 353 figure 13.16 sample multiprocessor se rial reception flowchart (2)......................................... 354 figure 13.17 data format in synchrono us communication (f or lsb-first) ............................. 355 figure 13.18 sample sci in itialization flowchart ...................................................................... 356 figure 13.19 sample sci transmission oper ation in clocked synchronous mode ................... 357 figure 13.20 sample serial transmission flowchart .................................................................. 358 figure 13.21 example of sci operation in reception ................................................................ 359 figure 13.22 sample serial reception flowchart ....................................................................... 360 figure 13.23 sample flowchart of simultaneous serial transmit and receive operations ....... 362 figure 13.24 schematic diagram of sm art card interface pin connections............................... 363 figure 13.25 normal smart ca rd interface data format ............................................................ 364 figure 13.26 direct convention (sdir = sinv = o/ e = 0) ....................................................... 364 figure 13.27 inverse convention (sdir = sinv = o/ e = 1)...................................................... 364 figure 13.28 receive data sa mpling timing in smart card mode (using clock of 372 times the transfer rate)........................................................................................ 366 figure 13.29 retransfer operation in sci transmit mode ......................................................... 368 figure 13.30 tend flag generation timi ng in transmission operation .................................. 369 figure 13.31 example of transmission processing flow............................................................ 370
rev. 5.00 sep. 01, 2009 page xlii of l rej09b0071-0500 figure 13.32 retransfer operation in sci receive mode ........................................................... 372 figure 13.33 example of reception processing flow................................................................. 372 figure 13.34 timing for fixi ng clock output level................................................................... 373 figure 13.35 clock halt and restart procedure .......................................................................... 374 figure 13.36 example of clocked s ynchronous transmi ssion by dtc ..................................... 377 figure 13.37 sample flowchart for m ode transition during transmission................................ 379 figure 13.38 asynchronous transmi ssion using internal clock ................................................ 379 figure 13.39 synchronous transmi ssion using intern al clock .................................................. 380 figure 13.40 sample flowchart for mode transition during reception ..................................... 380 figure 13.41 operation when switching from sck pin function to po rt pin function ............. 381 figure 13.42 operation when switching from sck pin function to port pin function (example of preventing low-level output).......................................................... 382 section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) figure 14.1 block diagram of i 2 c bus interface....................................................................... 385 figure 14.2 i 2 c bus interface connections (example: this lsi as master) ............................. 386 figure 14.3 i 2 c bus data formats (i 2 c bus formats) ............................................................... 406 figure 14.4 i 2 c bus data format (clocked synchronous serial format) ................................. 406 figure 14.5 i 2 c bus timing....................................................................................................... 407 figure 14.6 flowchart for iic initialization (example)............................................................. 408 figure 14.7 flowchart for master transmit mode (example)................................................... 409 figure 14.8 example of master transmit mode operation timing (mls = wait = 0).......... 411 figure 14.9 example of master transmit mode stop condition generation timing (mls = wait = 0) ................................................................................................ 412 figure 14.10 flowchart for master receive mode (receiving multiple bytes) (wait = 1) (example)............................................................................................................... 413 figure 14.11 flowchart for master receive mode (receiving 1 byte) (wait = 1) (example)............................................................................................................... 414 figure 14.12 example of master receive m ode operation timing (mls = ackb = 0, wait = 1).............................................................................................................. 416 figure 14.13 example of master receive mode stop condition generation timing (mls = ackb = 0, wait = 1)............................................................................. 417 figure 14.14 flowchart for slave transmit mode (example)..................................................... 418 figure 14.15 example of slave receive mode operation timing (1) (mls = ackb = 0) ....... 420 figure 14.16 example of slave receive mode operation timing (2) (mls = ackb = 0) ....... 421 figure 14.17 sample flowchart for slave transmit mode.......................................................... 422 figure 14.18 example of slave transmit mode operation timing (mls = 0) .......................... 424 figure 14.19 iric setting ti ming and scl control................................................................... 425 figure 14.20 block diagram of noise cancellor ........................................................................ 427 figure 14.21 points for attention concer ning reading of master receive data........................ 433
rev. 5.00 sep. 01, 2009 page xliii of l rej09b0071-0500 figure 14.22 flowchart and timing of start condition instruction issuance for retransmission ....................................................................................................... 435 figure 14.23 timing of stop condition issuance........................................................................ 436 figure 14.24 iric flag clearance in wait = 1 status .............................................................. 436 figure 14.25 icdr read and iccr acce ss timing in slave transmit mode............................ 437 figure 14.26 trs bit setting timing in slave mode ................................................................. 438 figure 14.27 diagram of erroneous oper ation when arbitration is lost ................................... 440 figure 14.28 timing of iric flag clearing during wait operation ........................................... 441 section 15 a/d converter figure 15.1 block diagra m of a/d converter .......................................................................... 444 figure 15.2 access to addr (when reading h'aa40)........................................................... 450 figure 15.3 example of a/d converter operation (single mode, channel 1 selected) ........... 452 figure 15.4 example of a/d converter operation (scan mode, channels an0 to an2 selected)................................................................................................................. 453 figure 15.5 a/d conve rsion ti ming......................................................................................... 454 figure 15.6 external tr igger input timing ............................................................................... 456 figure 15.7 a/d conversion accu racy definitions (1)............................................................. 458 figure 15.8 a/d conversion accu racy definitions (2)............................................................. 458 figure 15.9 example of analog input circuit ........................................................................... 459 figure 15.10 example of analog input protection circuit.......................................................... 461 figure 15.11 analog input pi n equivalent circuit ...................................................................... 461 section 16 d/a converter figure 16.1 block diagra m of d/a converter .......................................................................... 463 figure 16.2 d/a converter operation ex ample ........................................................................ 467 section 17 lcd controller/driver.....................................................................469 figure 17.1 block diagram of lcd controller/driver ............................................................. 470 figure 17.2 a waveform 1/2 duty 1/2 vias.............................................................................. 480 figure 17.3 handling of lcd drive po wer supply when us ing 1/2 duty ............................... 482 figure 17.4 lcd ram map (1/4 duty).................................................................................... 484 figure 17.5 lcd ram map (1/3 duty).................................................................................... 484 figure 17.6 lcd ram map (1/2 duty).................................................................................... 485 figure 17.7 lcd ram map (static mode) .............................................................................. 485 figure 17.8 output waveforms for e ach duty cycle (a waveform)....................................... 486 figure 17.9 output waveforms for each duty cycle (b waveform) ....................................... 487 figure 17.10 connection when triple step-up voltage circuit used (supported only by the h8s/2268 group) ............................................................................................. 489 figure 17.11 example of low-power-co nsumption lcd drive operation ............................... 491 figure 17.12 connection of external split-resistance................................................................ 492
rev. 5.00 sep. 01, 2009 page xliv of l rej09b0071-0500 section 18 dtmf generation circuit figure 18.1 dtmf frequencies ................................................................................................ 493 figure 18.2 dtmf generati on circuit diagram ....................................................................... 494 figure 18.3 toned pin output equivalent circuit.................................................................. 497 figure 18.4 toned pin output waveform (row or column group alone)........................... 497 figure 18.5 example of ha16808ant connection ................................................................. 499 section 20 rom ................................................................................................503 figure 20.1 block diagram of flash memory........................................................................... 504 figure 20.2 flash memory state transitions............................................................................. 505 figure 20.3 boot mode.......................................................................................................... .... 506 figure 20.4 user program mode (exa mple).............................................................................. 507 figure 20.5 flash memory block configuration (h8s/2268)................................................... 509 figure 20.6 flash memory block confi guration (h8s/2266 and h8s/2265) ........................... 510 figure 20.7 programming/erasing flowchar t example in user program mode....................... 521 figure 20.8 flowchart for flash memory emulation in ram .................................................. 522 figure 20.9 example of ram overlap operation..................................................................... 524 figure 20.10 program/program-verify flowchart ...................................................................... 526 figure 20.11 erase/erase-verify flowchart ................................................................................ 528 figure 20.12 socket adapter pin correspondence diagram ....................................................... 531 figure 20.13 power-on/off timing (boot mode) ...................................................................... 535 figure 20.14 power-on/off timi ng (user program mode) ........................................................ 536 figure 20.15 mode transition timing (example: boot mode user mode ? user program mode) ...................................................................................................... 537 section 21 clock pulse generator figure 21.1 block diagram of clock pulse generator .............................................................. 539 figure 21.2 connection of crystal resonator (example).......................................................... 543 figure 21.3 crystal resonator equivalent circuit ..................................................................... 544 figure 21.4 external cloc k input (exa mples) ........................................................................... 544 figure 21.5 external cl ock input timing.................................................................................. 546 figure 21.6 external clock sw itching circuit (examples) ....................................................... 546 figure 21.7 external clock sw itching timing (examples)....................................................... 547 figure 21.8 example connection of 32.768-khz crystal resonator......................................... 548 figure 21.9 equivalence circuit for 32.768-khz crystal resonator ......................................... 548 figure 21.10 pin handling when subclock not required.......................................................... 549 figure 21.11 note on board design of oscillator circuit ........................................................... 550 section 22 power-down modes figure 22.1 mode transition diagram ...................................................................................... 554 figure 22.2 medium-speed mode tr ansition and clearance timing ....................................... 561
rev. 5.00 sep. 01, 2009 page xlv of l rej09b0071-0500 figure 22.3 software standby m ode applicati on exampl e ...................................................... 564 figure 22.4 hardware st andby mode timing ........................................................................... 565 section 23 power supply circuit figure 23.1 power supply connections when internal power supply step-down circuit is used........................................................................................................................ 57 1 section 25 electrical characteristics figure 25.1 power supply voltage and operating ranges (1).................................................. 597 figure 25.1 power supply voltage and operating ranges (2).................................................. 598 figure 25.2 output load circuit ............................................................................................... 6 10 figure 25.3 output load circuit ............................................................................................... 6 31 figure 25.4 oscillator settling timing ...................................................................................... 638 figure 25.5 reset input timing................................................................................................. 638 figure 25.6 interrupt input timing............................................................................................ 6 39 figure 25.7 tpu cloc k input ti ming........................................................................................ 639 figure 25.8 8-bit timer clock input timing ............................................................................ 639 figure 25.9 sck cloc k input ti ming ....................................................................................... 639 figure 25.10 sci input/o utput timing (clock synchronous mode) .......................................... 640 figure 25.11 i 2 c bus interface input/output timing (option).................................................... 640 figure 25.12 toned load circuit (supp orted only by th e h8s/2268 group) ......................... 641 appendix c package dimensions......................................................................650 figure c.1 tfp-100b and tfp-100bv package dimensions (h8s/2268 group only).......... 650 figure c.2 tfp-100g and tfp- 100gv package dimensions ................................................. 651 figure c.3 fp-100b and fp-100b v package dimensions ...................................................... 652
rev. 5.00 sep. 01, 2009 page xlvi of l rej09b0071-0500 tables section 1 overview table 1.1 pin functions..............................................................................................................7 section 2 cpu table 2.1 instruction classification..........................................................................................29 table 2.2 operation notation...................................................................................................30 table 2.3 data transfer instructions ........................................................................................31 table 2.4 arithmetic operations instructions (1).....................................................................32 table 2.4 arithmetic operations instructions (2).....................................................................33 table 2.5 logic operations instructions ..................................................................................34 table 2.6 shift instructions ......................................................................................................34 table 2.7 bit manipulation instructions (1) .............................................................................35 table 2.7 bit manipulation instructions (2) .............................................................................36 table 2.8 branch instructions ..................................................................................................37 table 2.9 system control instructions .....................................................................................38 table 2.10 block data transfer instructions..............................................................................39 table 2.11 addressing modes....................................................................................................41 table 2.12 absolute address access ranges ............................................................................42 table 2.13 effective address calculation (1) ............................................................................45 table 2.13 effective address calculation (2) ............................................................................46 section 3 mcu operating modes table 3.1 mcu operating mode selection..............................................................................55 section 4 exception handling table 4.1 exception types and priority ...................................................................................59 table 4.2 exception handling vector table ............................................................................60 table 4.3 status of ccr and exr after trace exception handling........................................63 table 4.4 status of ccr and exr after trap instruction exception handling .......................64 section 5 interrupt controller table 5.1 pin configuration .....................................................................................................70 table 5.2 interrupt sources, vector addresse s, and interrupt priorities ..................................85 table 5.3 interrupt control modes...........................................................................................89 table 5.4 interrupts selected in each in terrupt control mode (1)...........................................90 table 5.5 interrupts selected in each in terrupt control mode (2)...........................................90 table 5.6 operations and control si gnal functions in each in terrupt control mode .............91 table 5.7 interrupt response times (states)............................................................................97
rev. 5.00 sep. 01, 2009 page xlvii of l rej09b0071-0500 table 5.8 number of states in interrupt handling routine execution status..........................98 table 5.9 interrupt source selecti on and clear control......................................................... 100 section 8 data transfer controller (dtc) table 8.1 activation source and dtcer clearing................................................................ 122 table 8.2 interrupt sources, dtc vector addresses, and corresponding dtces ................ 125 table 8.3 register information in normal mode ................................................................... 128 table 8.4 register information in repeat mode .................................................................... 129 table 8.5 register information in block transf er mode ....................................................... 130 table 8.6 dtc execution status ............................................................................................ 134 table 8.7 number of states required fo r each execution status .......................................... 134 section 9 i/o ports table 9.1 h8s/2268 group port f unctions (1)....................................................................... 140 table 9.1 h8s/2264 group port f unctions (2)....................................................................... 143 table 9.2 input pull-up mos states (port j)......................................................................... 173 table 9.3 examples of ways to handle unused input pins................................................... 184 section 10 16-bit timer pulse unit (tpu) table 10.1 tpu functions........................................................................................................ 186 table 10.2 tpu pins ................................................................................................................ 190 table 10.3 cclr0 to cclr2 (channel 0) (h8s/2268 group only) ...................................... 193 table 10.4 cclr0 to cclr2 (cha nnels 1 a nd 2) ................................................................... 193 table 10.5 tpsc0 to tpsc2 (channel 0) (h8s/2268 grou p only) ........................................ 194 table 10.6 tpsc0 to tpsc2 (channel 1)................................................................................ 194 table 10.7 tpsc0 to tpsc2 (channel 2)................................................................................ 195 table 10.8 md0 to md3.......................................................................................................... 197 table 10.9 tiorh_0 (channel 0) (h 8s/2268 group only).................................................... 199 table 10.10 tiorl_0 (channel 0) (h 8s/2268 group only) .................................................... 200 table 10.11 tior_1 (channel 1)............................................................................................... 201 table 10.12 tior_2 (channel 2)............................................................................................... 202 table 10.13 tiorh_0 (channel 0) (h 8s/2268 group only).................................................... 203 table 10.14 tiorl_0 (channel 0) (h 8s/2268 group only) .................................................... 204 table 10.15 tior_1 (channel 1)............................................................................................... 205 table 10.16 tior_2 (channel 2)............................................................................................... 206 table 10.17 register combinations in buffer operation........................................................... 225 table 10.18 pwm output registers and output pins................................................................ 229 table 10.19 phase counting mode clock input pins................................................................. 233 table 10.20 up/down-count conditions in phase counting mode 1 ....................................... 234 table 10.21 up/down-count conditions in phase counting mode 2 ....................................... 235 table 10.22 up/down-count conditions in phase counting mode 3 ....................................... 236
rev. 5.00 sep. 01, 2009 page xlviii of l rej09b0071-0500 table 10.23 up/down-count conditions in phase counting mode 4 ....................................... 237 table 10.24 tpu interrupts........................................................................................................ 238 section 11 8-bit timers table 11.1 pin configuration ................................................................................................... 259 table 11.2 8-bit timer interrupt sources ................................................................................ 274 table 11.3 timer output priorities .......................................................................................... 277 table 11.4 switching of internal clock and tcnt operation................................................. 278 section 12 watchdog timer (wdt) table 12.1 wdt interrupt source............................................................................................ 299 section 13 serial communication interface (sci) table 13.1 pin configuration ................................................................................................... 307 table 13.2 the relationships between the n setting in brr and bit rate b ......................... 326 table 13.3 brr settings for various bit ra tes (asynchronous mode) (1)............................. 327 table 13.3 brr settings for various bit ra tes (asynchronous mode) (2)............................. 328 table 13.3 brr settings for various bit ra tes (asynchronous mode) (3)............................. 329 table 13.3 brr settings for various bit ra tes (asynchronous mode) (4)............................. 330 table 13.4 maximum bit rate for each frequency (asynchronous mode)............................ 330 table 13.5 maximum bit rate with external cl ock input (asynchronous mode).................. 331 table 13.6 brr settings for various bit rates (clocked synchronous mode) ...................... 332 table 13.7 maximum bit rate with external clock input (clocked synchronous mode)...... 332 table 13.8 examples of bit rate for various brr settings (smart card interface mode) (when n = 0 a nd s = 372) ...................................................................................... 333 table 13.9 maximum bit rate at various freque ncies (smart card interface mode) (when s = 372) ...................................................................................................... 333 table 13.10 serial transfer formats (asynchronous mode) ..................................................... 339 table 13.11 ssr status flags and receive data handling........................................................ 346 table 13.12 interrupt sources of serial communication interface mode.................................. 375 table 13.13 interrupt sources in smart card interface mode.................................................... 376 section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) table 14.1 pin configuration ................................................................................................... 386 table 14.2 transfer format...................................................................................................... 391 table 14.3 i 2 c transfer rate .................................................................................................... 393 table 14.4 flags and transfer states ....................................................................................... 400 table 14.5 flags and transfer states ....................................................................................... 426 table 14.6 iic interrupt source ............................................................................................... 429 table 14.7 i 2 c bus timing (scl a nd sda output) ................................................................ 430 table 14.8 permissible scl rise time (t sr ) values ................................................................. 431
rev. 5.00 sep. 01, 2009 page xlix of l rej09b0071-0500 table 14.9 i 2 c bus timing (with maximum influence of t sr /t sf )............................................... 432 section 15 a/d converter table 15.1 pin configuration ................................................................................................... 445 table 15.2 analog input channels and corresponding addr registers................................ 446 table 15.3 a/d conversion time (single m ode) .................................................................... 455 table 15.4 a/d conversion time (scan mode)....................................................................... 455 table 15.5 a/d converter interrupt source ............................................................................. 456 table 15.6 analog pin speci fications ...................................................................................... 461 section 16 d/a converter table 16.1 pin configuration ................................................................................................... 464 table 16.2 d/a conversion control ........................................................................................ 466 section 17 lcd controller/driver table 17.1 pin configuration ................................................................................................... 471 table 17.2 duty cycle and common function selection ........................................................ 473 table 17.3 segment driver selecti on (1) (h8s/ 2268 group ) .................................................. 474 table 17.4 segment driver selecti on (2) (h8s/ 2264 group ) .................................................. 475 table 17.5 frame frequency selection .................................................................................... 477 table 17.6 output levels ......................................................................................................... 488 table 17.7 power-down modes and display operation.......................................................... 490 section 18 dtmf generation circuit table 18.1 pin configuration ................................................................................................... 494 table 18.2 frequency deviation between dtmf ou tput signals and typical signals........... 498 section 20 rom table 20.1 differences between boot mode and user program mode.................................... 505 table 20.2 pin configuration ................................................................................................... 511 table 20.3 setting on-board programming modes................................................................. 518 table 20.4 boot mode operation............................................................................................. 520 table 20.5 system clock frequencies for which automatic adjustment of lsi bit rate is possible .................................................................................................................. 520 table 20.6 flash memory operating states ............................................................................. 532 table 20.7 registers present in f-ztat version but absent in masked rom version ........ 538 section 21 clock pulse generator table 21.1 damping resistance value .................................................................................... 544 table 21.2 crystal resonator characteristics........................................................................... 544 table 21.3 external clock input conditions ............................................................................ 545
rev. 5.00 sep. 01, 2009 page l of l rej09b0071-0500 table 21.4 external clock input conditions (dut y adjustment circuit not used)................. 545 section 22 power-down modes table 22.1 lsi internal states in each mode........................................................................... 552 table 22.2 low power dissipation mode transition conditions ............................................ 555 table 22.3 oscillation settling time settings.......................................................................... 563 section 25 electrical characteristics table 25.1 absolute maximum ratings................................................................................... 599 table 25.2 dc characteristics (1) ............................................................................................ 600 table 25.2 dc characteristics (2) ............................................................................................ 602 table 25.2 dc characteristics (3) ............................................................................................ 604 table 25.2 dc characteristics (4) ............................................................................................ 606 table 25.3 permissible out put currents .................................................................................. 608 table 25.4 bus drive characteristics (1) ................................................................................. 609 table 25.4 bus drive characteristics (2) ................................................................................. 610 table 25.5 clock timing.......................................................................................................... 611 table 25.6 control signal timing............................................................................................ 612 table 25.7 timing of on-chip pe ripheral m odules................................................................. 613 table 25.8 i 2 c bus timing....................................................................................................... 614 table 25.9 a/d conversion characteristics ............................................................................. 615 table 25.10 d/a conversion characteristics ............................................................................. 616 table 25.11 lcd characteristics ............................................................................................... 617 table 25.12 dtmf characteristics ............................................................................................ 618 table 25.13 flash memory characteristics................................................................................ 619 table 25.14 absolute maximum ratings................................................................................... 621 table 25.15 dc characteristics (1) ............................................................................................ 622 table 25.15 dc characteristics (2) ............................................................................................ 624 table 25.15 dc characteristics (3) ............................................................................................ 625 table 25.15 dc characteristics (4) ............................................................................................ 627 table 25.16 permissible out put currents .................................................................................. 629 table 25.17 bus drive characteristics (1) ................................................................................. 630 table 25.17 bus drive characteristics (2) ................................................................................. 631 table 25.18 clock timing.......................................................................................................... 632 table 25.19 control signal timing............................................................................................ 633 table 25.20 timing of on-chip pe ripheral m odules................................................................. 634 table 25.21 i 2 c bus timing....................................................................................................... 635 table 25.22 a/d conversion characteristics ............................................................................. 636 table 25.23 lcd characteristics ............................................................................................... 637
section 1 overview rev. 5.00 sep. 01, 2009 page 1 of 656 rej09b0071-0500 section 1 overview 1.1 features ? high-speed h8s/2000 central processing unit with an internal 16-bit architecture ? upward-compatible with h8/300 and h8/300h cpus on an object level ? sixteen 16-bit general registers ? 65 basic instructions ? various peripheral functions ? interrupt controller ? pc break controller (supported only by the h8s/2268 group) ? data transfer controller (dtc) (supported only by the h8s/2268 group) ? 16-bit timer-pulse unit (tpu) ? 8-bit timer (tmr) ? watchdog timer (wdt) ? serial communication interface (sci) ? i 2 c bus interface (iic) (supported as an option by h8s/2264 group) ? a/d converter ? d/a converter (supported only by the h8s/2268 group) ? lcd controller/driver ? dtmf generation circuit (supported only by the h8s/2268 group) ? on-chip memory h8s/2268 group: rom model rom ram remarks hd64f2268 256 kbytes 16 kbytes flash memory version hd64f2266 128 kbytes 8 kbytes hd64f2265 128 kbytes 4 kbytes h8s/2264 group: rom model rom ram remarks hd6432264 128 kbytes 4 kbytes hd6432264w 128 kbytes 4 kbytes masked rom version hd6432262 64 kbytes 2 kbytes hd6432262w 64 kbytes 2 kbytes
section 1 overview rev. 5.00 sep. 01, 2009 page 2 of 656 rej09b0071-0500 ? general i/o ports ? i/o pins: 67 (supported only by the h8s/2268 group) 51 (supported only by the h8s/2264 group) ? input-only pins: 11 ? supports various power-down states ? compact package package code * 2 body size pin pitch tqfp-100 * 1 tfp-100b, tfp-100bv 14.0 14.0 mm 0.5 mm tqfp-100 tfp-100g, tfp-100gv 12.0 12.0 mm 0.4 mm qfp-100 fp-100b, fp-100bv 14.0 14.0 mm 0.5 mm notes: 1. supported only by the h8s/2268 group. 2. package codes ending in the letter v designate pb-free product.
section 1 overview rev. 5.00 sep. 01, 2009 page 3 of 656 rej09b0071-0500 1.2 internal block diagram figure 1.1 shows the internal block diagram of the h8s/2268 group and figure 1.2 shows that of the h8s/2264 group. internal data bus cvcc vcc vss vss v1 v2 v3 c1 c2 vref avcc avss rom pc break controller (2 channels) ram tpu (3 channels) md2 md1 extal xtal osc1 osc2 stby res nmi fwe h8s/2000 cpu dtc interrupt controller pn7 / seg40 pn6 / seg3 9 pn5 / seg38 pn4 / seg37 pn3 / seg36 pn2 / seg35 pn1 / seg34 pn0 / seg33 port n p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 port 4 p10 / tioca0 p11 / tiocb0 p12 / tiocc0 / tclka p13 / tiocd0 / tclkb p14 / tioca1/ irq0 p15 / tiocb1 / tclkc p16 / tioca2/ irq1 p17 / tiocb2/ tclkd port 1 p 9 6/an8/da0 p 9 7/an 9 /da1 port 9 internal address bus pl7 / seg24 pl6 / seg23 pl5 / seg22 pl4 /seg21 pl3 / seg20 pl2 / seg1 9 pl1 / seg18 pl0 / seg17 pk7 / seg16 pk6 / seg15 pk5 / seg14 pk4 /seg13 pk3 / seg12 pk2 / seg11 pk1 / seg10 pk0 / seg 9 pj7 / wkp7 /seg8 pj6 / wkp6 /seg7 pj5 / wkp5 /seg6 pj4 / wkp4 /seg5 pj3 / wkp3 /seg4 pj2 / wkp2 /seg3 pj1 / wkp1 /seg2 pj0 / wkp0 /seg1 pm7 / seg32 pm6 / seg31 pm5 / seg30 pm4 /seg2 9 pm3 / seg28 pm2 / seg27 pm1 / seg26 pm0 / seg25 ph7/toned/tmci4 ph3/com4 ph2/com3 ph1/com2 ph0/com1 pf3/ adtrg / irq3 p35/sck1/scl0/ irq5 p34/rxd1/sda0 p33/txd1/scl1 p32/sck0/sda1/ irq4 p31/rxd0 p30/txd0 p70/tmri01/tmci01 p71/tmri23/tmci23 p72/tmo0 p73/tmo1 p74/tmo2 p75/tmo3/sck2 p76/rxd2 p77/txd2 port 7 port 3 port f lcd (40seg/4com) iic (2 channels) sci (3 channels) a/d converter(10 channels) 8 bit timer (4 channels+4 channels) d/a converter(2 channels) wdt0 wdt1 (sub clock) sub clock pulse generator system clock pulse generator dtmf peripheral data bus peripheral address bus port h port j port k port l port m bus controller figure 1.1 internal block diagram of h8s/2268 group
section 1 overview rev. 5.00 sep. 01, 2009 page 4 of 656 rej09b0071-0500 internal data bus cvcc v cc v ss v ss v1 v 2 v3 vref avcc avss rom ram tpu (2 channels) md2 md1 extal xtal osc1 osc2 stby res nmi fwe h8s/2000 cpu interrupt controller seg40 seg3 9 seg38 seg37 seg36 seg35 seg34 seg33 p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 port 4 p10 p11 p12 / tclka p13 / tclkb p14 / tioca1/ irq0 p15 / tiocb1 / tclkc p16 / tioca2/ irq1 p17 / tiocb2 port 1 p 9 6/an8 p 9 7/an 9 port 9 internal address bus pl7 / seg24 pl6 / seg23 pl5 / seg22 pl4 /seg21 pl3 / seg20 pl2 / seg1 9 pl1 / seg18 pl0 / seg17 pk7 / seg16 pk6 / seg15 pk5 / seg14 pk4 /seg13 pk3 / seg12 pk2 / seg11 pk1 / seg10 pk0 / seg 9 pj7 / wkp7 /seg8 pj6 / wkp6 /seg7 pj5 / wkp5 /seg6 pj4 / wkp4 /seg5 pj3 / wkp3 /seg4 pj2 / wkp2 /seg3 pj1 / wkp1 /seg2 pj0 / wkp0 /seg1 seg32 seg31 seg30 seg2 9 seg28 seg27 seg26 seg25 ph7 ph3/com4 ph2/com3 ph1/com2 ph0/com1 pf3/ adtrg / irq3 p35/sck1/scl0 p34/rxd1/sda0 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 p70/tmri01/tmci01 p7 1 p72/tmo0 p73/tmo1 p74 p75/sck2 p76/rxd2 p77/txd2 port 7 port 3 port f lcd (40seg/4com) iic (1 channel) (option) sci (3 channels) a/d converter (10 channels) 8 bit timer (2 channels) wdt0 wdt1 (sub clock) sub clock pulse generator system clock pulse generator peripheral data bus peripheral address bus port h port j port k port l bus controller peripheral address bus figure 1.2 internal block diagram of h8s/2264 group
section 1 overview rev. 5.00 sep. 01, 2009 page 5 of 656 rej09b0071-0500 1.3 pin arrangement figure 1.3 shows the pin arrangement of the h8s/2268 group and figure 1.4 shows that of the h8s/2264 group. p30/txd0 p31/rxd0 p32/sck0/sda1/ irq4 p33/txd1/scl1 p34/rxd1/sda0 p35/sck1/scl0/ irq5 pf3/ adtrg / irq3 c2 c1 v3 v2 v1 ph3/com4 ph2/com3 ph1/com2 ph0/com1 pn7/seg40 pn6/seg3 9 pn5/seg38 pn4/seg37 pn3/seg36 pn2/seg35 pn1/seg34 pn0/seg33 pm7/seg32 76 77 78 7 9 80 81 82 83 84 85 86 87 88 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 99 100 50 4 9 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9 28 27 26 p70/tmri01/tmci01 p71/tmri23/tmci23 p72/tmo0 p73/tmo1 p74/tmo2 p75/tmo3/sck2 p76/rxd2 p77/txd2 md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 ph7/toned/tmci4 avcc vref p40/an0 p41/an1 75 74 73 72 71 70 6 9 68 67 66 65 64 63 62 61 60 5 9 58 57 56 55 54 53 52 51 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p 9 6/an8/da0 p 9 7/an 9 /da1 p17/tiocb2/tclkd p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tiocd0/tclkb p12/tiocc0/tclka p11/tiocb0 p10/tioca0 pj0/ wkp0 /seg1 pj1/ wkp1 /seg2 pj2/ wkp2 /seg3 pj3/ wkp3 /seg4 pj4/ wkp4 /seg5 pj5/ wkp5 /seg6 pj6/ wkp6 /seg7 pj7/ wkp7 /seg8 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 25 pm6/seg31 pm5/seg30 pm4/seg2 9 pm3/seg28 pm2/seg27 pm1/seg26 pm0/seg25 pl7/seg24 pl6/seg23 pl5/seg22 pl4/seg21 pl2/seg1 9 pl1/seg18 pl0/seg17 pk7/seg16 pk6/seg15 pk5/seg14 pk4/seg13 pk3/seg12 pk1/seg10 pk0/seg 9 cvcc pl3/seg20 vss pk2/seg11 fp-100b fp-100bv tfp-100b tfp-100bv tfp-100g tfp-100gv (top view) figure 1.3 pin arrangement of h8s/2268 group
section 1 overview rev. 5.00 sep. 01, 2009 page 6 of 656 rej09b0071-0500 p30/txd0 p31/rxd0 p32/sck0/ irq4 p33/txd1 p34/rxd1/sda0 p35/sck1/scl0 pf3/ adtrg / irq3 nc * nc * v3 v2 v1 ph3/com4 ph2/com3 ph1/com2 ph0/com1 seg40 seg3 9 seg38 seg37 seg36 seg35 seg34 seg33 seg32 76 77 78 7 9 80 81 82 83 84 85 86 87 88 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 99 100 50 4 9 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9 28 27 26 p70/tmri01/tmci01 p71 p72/tmo0 p73/tmo1 p74 p75/sck2 p76/rxd2 p77/txd2 md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 ph7 avcc vref p40/an0 p41/an1 75 74 73 72 71 70 6 9 68 67 66 65 64 63 62 61 60 5 9 58 57 56 55 54 53 52 51 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p 9 6/an8 p 9 7/an 9 p17/tiocb2 p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tclkb p12/tclka p11 p10 pj0/ wkp0 /seg1 pj1/ wkp1 /seg2 pj2/ wkp2 /seg3 pj3/ wkp3 /seg4 pj4/ wkp4 /seg5 pj5/ wkp5 /seg6 pj6/ wkp6 /seg7 pj7/ wkp7 /seg8 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 25 seg31 seg30 seg2 9 seg28 seg27 seg26 seg25 pl7/seg24 pl6/seg23 pl5/seg22 pl4/seg21 pl2/seg1 9 pl1/seg18 pl0/seg17 pk7/seg16 pk6/seg15 pk5/seg14 pk4/seg13 pk3/seg12 pk1/seg10 pk0/seg 9 cvcc pl3/seg20 vss pk2/seg11 fp-100b fp-100bv tfp-100g tfp-100gv (top view) note: * the nc pin should be open. figure 1.4 pin arrangement of h8s/2264 group
section 1 overview rev. 5.00 sep. 01, 2009 page 7 of 656 rej09b0071-0500 1.4 pin functions table 1.1 lists the pins functions. table 1.1 pin functions type symbol pin no. i/o function power supply vcc 62 input power supply pin. connect this pin to the system power supply. cvcc 12 input connect this pin to vss via a capacitor (h8s/2268 group: 0.1 f/0.2 f and h8s/2264 group: 0.2 f) for voltage stabilization. note that applying a voltage exceeding 4.3 v, the absolute maximum rating, to the cvcc pin may cause fatal damages on this lsi. do not connect the power supply to the cvcc pin. see section 23, power supply circuit, for connecting examples. v3 v2 v1 85 86 87 input power supply pins for the lcd controller/driver. with an internal power supply division resistor, these pins are normally left open. power supply should be within the range of vcc v1 v2 v3 vss. when the triple step-up voltage circuit * 1 is used, the v3 pin is used for the lcd input reference power supply. vss 14 64 input ground pins. connect this pin to the system power supply (0 v). clock xtal 63 input extal 65 input for connection to a crystal resonator. this pin can be also used for external clock input. for examples of crystal resonator connection and external clock input, see section 21, clock pulse generator. osc1 58 input osc2 57 input connects to a 32.768 khz crystal resonator. see section 21, clock pulse generator, for typical connection diagrams for a crystal resonator. operating mode control md2, md1 67 56 input sets the operating mode. inputs at these pins should not be changed during operation. be sure to fix the levels of the mode pins (md2, md1) by pull-down or pull-up, except for mode changing.
section 1 overview rev. 5.00 sep. 01, 2009 page 8 of 656 rej09b0071-0500 type symbol pin no. i/o function system control res * 2 59 input reset input pin. when this pin is low, the chip enters in the power-on reset state. stby * 2 61 input when this pin is low, a transition is made to hardware standby mode. fwe 66 input enables/disables programming the flash memory. interrupts nmi * 2 60 input nonmaskable interrupt pin. if this pin is not used, it should be fixed-high. irq5 * 1 irq4 irq3 irq1 irq0 81 78 82 40 38 input these pins request a maskable interrupt. wkp7 to wkp0 26 to 33 input these pins request a wakeup interrupt. this interrupt is maskable. 16-bit timer- pulse unit (tpu) tclkd * 1 tclkc tclkb tclka 41 39 37 36 input these pins input an external clock. tioca0 * 1 tiocb0 * 1 tiocc0 * 1 tiocd0 * 1 34 35 36 37 input/ output pins for the tgra_0 to tgrd_0 input capture input or output compare output, or pwm output. tioca1 tiocb1 38 39 input/ output pins for the tgra _ 1 and tgrb _ 1 input capture input or output compare output, or pwm output. tioca2 tiocb2 40 41 input/ output pins for the tgra _ 2 and tgrb _ 2 input capture input or output compare output, or pwm output. 8-bit timer tmo3 * 1 tmo2 * 1 tmo1 tmo0 70 71 72 73 output compare-match output pins tmci23 * 1 tmci01 tmci4 * 1 74 75 55 input pins for external clock input to the counter tmri23 * 1 tmri01 74 75 input counter reset input pins.
section 1 overview rev. 5.00 sep. 01, 2009 page 9 of 656 rej09b0071-0500 type symbol pin no. i/o function txd2 txd1 txd0 68 79 76 output data output pins rxd2 rxd1 rxd0 69 80 77 input data input pins serial communi- cation interface (sci)/smart card interface sck2 sck1 sck0 70 81 78 input/ output clock input/output pins. sck1 outputs nmos push-pull. scl1 * 1 scl0 79 81 input/ output i 2 c clock input/output pins. these pins drive bus. the output of scl0 is nmos open drain. i 2 c bus interface * 3 sda1 * 1 sda0 78 80 input/ output i 2 c data input/output pins. these pins drive bus. the output of sda0 is nmos open drain. a/d converter an9 to an0 43 to 52 input analog input pins adtrg 82 input pin for input of an external trigger to start a/d conversion d/a converter * 1 da1 da0 43 44 output analog output pins for the d/a converter * 1 . a/d converter, d/a converter * 1 avcc 54 input power supply pin for the a/d converter, d/a converter * 1 and dtmf generation circuit * 1 . if none of the a/d converter, d/a converter * 1 and dtmf generation circuit * 1 is used, connect this pin to the system power supply (vcc level). avss 42 input ground pin for the a/d converter, d/a converter * 1 , and dtmf generator * 1 . connect this pin to the system power supply (0 v). vref 53 input reference voltage input pin for the a/d converter and d/a converter * 1 . if neither the a/d converter nor d/a converter * 1 is used, connect this pin to the system power supply (vcc level).
section 1 overview rev. 5.00 sep. 01, 2009 page 10 of 656 rej09b0071-0500 type symbol pin no. i/o function lcd controller/ driver seg40 to seg 1 92 to 100, 1 to 11, 13, 15 to 33 output lcd segment output pins com4 to com1 88 to 91 output lcd common output pins c2 * 1 c1 * 1 83 84 ? pins for the step-up voltage capacitor of the lcd drive power supply. dtmf generation circuit * 1 toned 55 output dtmf signal output pin. i/o ports p17 to p10 41 to 34 input/ output 8-bit i/o pins p35 to p30 81 to 76 input/ output 6-bit i/o pins p34 and p35 output nmos push-pull. p47 to p40 45 to 52 input 8-bit input pins p77 to p70 68 to 75 input/ output 8-bit i/o pins p97 p96 43 44 input 2-bit input pins pf3 82 input/ output 1-bit i/o pin ph7 55 input 1-bit input pin ph3 to ph0 88 to 91 input/ output 4-bit i/o pins pj7 to pj0 26 to 33 input/ output 8-bit i/o pins pk7 to pk0 18 to 25 input/ output 8-bit i/o pins pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 8 9 10 11 13 15 16 17 input/ output 8-bit i/o pins
section 1 overview rev. 5.00 sep. 01, 2009 page 11 of 656 rej09b0071-0500 type symbol pin no. i/o function i/o ports pm7 * 1 pm6 * 1 pm5 * 1 pm4 * 1 pm3 * 1 pm2 * 1 pm1 * 1 pm0 * 1 100 1 2 3 4 5 6 7 input/ output 8-bit i/o pins pn7 to pn0 * 1 92 to 99 input/ output 8-bit i/o pins notes: 1. supported only by the h8s/2268 group. 2. countermeasure against noise should be executed or may result in malfunction. 3. supported as an option by h8s/2264 group.
section 1 overview rev. 5.00 sep. 01, 2009 page 12 of 656 rej09b0071-0500
section 2 cpu rev. 5.00 sep. 01, 2009 page 13 of 656 rej09b0071-0500 section 2 cpu the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte linear ad dress space, and is ideal for realtime control. this section describes the h8s/2000 cpu. the us able modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. 2.1 features ? upward-compatible with h8/300 and h8/300h cpu ? can execute h8/300 and h8/300h cpu object programs ? general-register architecture ? sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers ? sixty-five basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacemen t [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes ? high-speed operation ? all frequently-used instructions execute in one or two states ? 8/16/32-bit register-register add/subtract: 1 state ? 8 8-bit register-register multiply: 12 states ? 16 8-bit register-register divide: 12 states cpus213a_000020020700
section 2 cpu rev. 5.00 sep. 01, 2009 page 14 of 656 rej09b0071-0500 ? 16 16-bit register-register multiply: 20 states ? 32 16-bit register-register divide: 20 states ? two cpu operating modes ? normal mode * ? advanced mode ? power-down state ? transition to power-down state by a sleep instruction ? cpu clock speed selection note: * normal mode is not available in this lsi. 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are shown below. ? register configuration ? the mac register is supported by the h8s/2600 cpu only. ? basic instructions ? the four instructions mac, clrmac, ldmac, and stmac are supported by the h8s/2600 cpu only. ? the number of execution states of the mulxu and mulxs instructions; execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 in addition, there are differences in address space, ccr and exr * register functions, and power- down modes, etc., depending on the model. note: * supported only by the h8s/2268 group.
section 2 cpu rev. 5.00 sep. 01, 2009 page 15 of 656 rej09b0071-0500 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements: ? more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. ? expanded address space ? normal mode supports the same 64-kbyt e address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. ? enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. 2.1.3 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements: ? additional control register ? one 8-bit control registers have been added. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast.
section 2 cpu rev. 5.00 sep. 01, 2009 page 16 of 656 rej09b0071-0500 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: norma l and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space. the mode is selected by the mode pins. 2.2.1 normal mode the exception vector table and stack have th e same structure as in the h8/300 cpu. ? address space linear access is provided to a ma ximum address space of 64 kbytes. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@?rn) or post-increment (@rn+) and a carry or borrow o ccurs, however, the value in the corresponding extended register (en) will be affected. ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. ? exception vector table and memory indirect branch addresses in normal mode the top area starting at h'0000 is allocated to the excep tion vector table. one branch address is stored per 16 bits. figure 2.1 shows the structure of the exception vector table in normal mode. for details of the exception vector table, see section 4, exception handling. the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. ? stack structure when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr) and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. exr is not pushed onto the stack in interrupt control mode 0. for details, see section 4, exception handling. note: * normal mode is not available in this lsi.
section 2 cpu rev. 5.00 sep. 01, 2009 page 17 of 656 rej09b0071-0500 h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'000 9 h'000a h'000b reset exception vector (reserved for system use) exception vector 1 exception vector 2 exception vector table figure 2.1 exception v ector table (normal mode) pc (16 bits) exr * 1 reserved * 1 * 3 ccr ccr * 3 pc (16 bits) sp sp (sp * 2 1. when exr is not used it is not stored on the stack. 2. sp when exr is not used. 3. lgnored when returning. notes: (b) exception handling (a) subroutine branch ) figure 2.2 stack stru cture in normal mode
section 2 cpu rev. 5.00 sep. 01, 2009 page 18 of 656 rej09b0071-0500 2.2.2 advanced mode ? address space linear access is provided to a maximum 16-mbyte address space. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. ? instruction set all instructions and addressing modes can be used. ? exception vector table and memory indirect branch addresses in advanced mode, the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c h'00000010 h'00000008 h'00000007 reserved reserved reset exception vector exception vector 3 exception vector table exception vector 1 figure 2.3 excep tion vector tabl e (advanced mode)
section 2 cpu rev. 5.00 sep. 01, 2009 page 19 of 656 rej09b0071-0500 the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits is a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. ? stack structure in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr * ) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. when exr * is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. note: * supported only by the h8s/2268 group. pc (24 bits) exr * 1 * 4 reserved * 1 * 3 * 4 ccr pc (24 bits) sp sp (sp * 2 reserved (a) subroutine branch (b) exception handling notes: 1. when exr is not used it is not stored on the stack. 2. sp when exr is not used (the h8s/2264 group sp always points here). 3. ignored when returning. 4. supported only by the h8s/2268 group. ) figure 2.4 stack stru cture in advanced mode
section 2 cpu rev. 5.00 sep. 01, 2009 page 20 of 656 rej09b0071-0500 2.3 address space figure 2.5 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in adva nced mode. the usable modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff 64 kbytes 16 mbytes program area data area (b) advanced mode (a) normal mode note: normal mode is not available in this lsi figure 2.5 memory map
section 2 cpu rev. 5.00 sep. 01, 2009 page 21 of 656 rej09b0071-0500 2.4 register configuration the h8s/2000 cpu has the internal registers shown in figure 2.6. there are two types of registers: general registers and control registers. control registers are a 24-bit program counter (pc), an 8- bit extended control register (exr * ), and an 8-bit condition code register (ccr). note: * supported only by the h8s/2268 group. ti2i1i0 exr * 1 76543210 pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp pc exr t i2 to i0 ccr i ui : stack pointer : program counter : extended control register * 1 : trace bit * 1 : interrupt mask bits * 1 : condition-code register * 1 : interrupt mask bit : user bit or interrupt mask bit * 2 : half-carry flag : user bit : negative flag : zero flag : overflow flag : carry flag er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h u n z v c general registers (rn) and extended registers (en) control registers (cr) legend: ---- notes: 1. supported only by the h8s/2268 group. 2. the interrupt mask bit is not available in this lsi. figure 2.6 cpu registers
section 2 cpu rev. 5.00 sep. 01, 2009 page 22 of 656 rej09b0071-0500 2.4.1 general registers the h8s/2000 cpu has eight 32-bit general register s. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figure 2.7 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general register s designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit 2egisters. the usage of each register can be selected independently. general register er7 has the function of stack poi nter (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.8 shows the stack. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.7 usage of general registers
section 2 cpu rev. 5.00 sep. 01, 2009 page 23 of 656 rej09b0071-0500 sp (er7) free area stack area figure 2.8 stack status 2.4.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) 2.4.3 extended control register (exr) (h8s/2268 group only) exr is an 8-bit register that manipulates the ldc, stc, andc, orc, and xorc instructions. when these instructions except for the stc instruction is executed, all interrupts including nmi will be masked for three states after execution is completed. bit bit name initial value r/w description 7 t 0 r/w trace bit when this bit is set to 1, a trace exception is generated each time an instruction is executed. when this bit is cleared to 0, instructions are executed in sequence. 6 to 3 ? 1 ? reserved these bits are always read as 1. 2 1 0 i2 i1 i0 1 1 1 r/w r/w r/w these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller.
section 2 cpu rev. 5.00 sep. 01, 2009 page 24 of 656 rej09b0071-0500 2.4.4 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z ), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 by hardware at the start of an exception-handling sequence. for details, refer to section 5, interrupt controller. 6 ui undefined r/w user bit or interrupt mask bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit cannot be used as an interrupt mask bit in this lsi. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
section 2 cpu rev. 5.00 sep. 01, 2009 page 25 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 initial values of cpu registers reset exception handling loads the cp u's program counter (pc) from the vector table, clears the trace bit in exr * to 0, and sets the interrupt mask bits in ccr and exr * to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. note: * supported only by the h8s/2268 group.
section 2 cpu rev. 5.00 sep. 01, 2009 page 26 of 656 rej09b0071-0500 2.5 data formats the h8s/2000 cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipul ation instructions operate on 1-bit da ta by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.9 shows the data formats in general registers. 70 70 msb lsb msb lsb 70 43 don't care don't care don't care 70 43 70 don't care 65432 710 70 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type register number data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.9 general re gister data formats (1)
section 2 cpu rev. 5.00 sep. 01, 2009 page 27 of 656 rej09b0071-0500 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb en rn ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format register number word data word data rn en longword data legend: ern figure 2.9 general re gister data formats (2)
section 2 cpu rev. 5.00 sep. 01, 2009 page 28 of 656 rej09b0071-0500 2.5.2 memory data formats figure 2.10 shows the data formats in memo ry. the h8s/2000 cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at th e preceding address. this also applies to instruction fetches. when er7 is used as an address register to access the stack, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m + 1 longword data address 2n address 2n + 1 address 2n + 2 address 2n + 3 data format figure 2.10 memory data formats
section 2 cpu rev. 5.00 sep. 01, 2009 page 29 of 656 rej09b0071-0500 2.6 instruction set the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function in table 2.1. table 2.1 instructio n classification function instructions size types data transfer mov b/w/l 5 pop * 1 , push * 1 w/l ldm * 5 , stm * 5 l movfpe * 3 , movtpe * 3 b arithmetic add, sub, cmp, neg b/w/l 19 operations addx, subx, daa, das b inc, dec b/w/l adds, subs l mulxu, divxu, mulxs, divxs b/w extu, exts w/l tas * 4 b logic operations and, or, xor, not b/w/l 4 shift shal, shar, shll, shlr, ro tl, rotr, rotxl, rotxr b/w/l 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b 14 branch bcc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 total: 65 legend: b: byte w: word l: longword notes: 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @-sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in this lsi. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. 5. only register er0 to er6 should be used when using the stm/ldm instruction.
section 2 cpu rev. 5.00 sep. 01, 2009 page 30 of 656 rej09b0071-0500 2.6.1 table of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the notation used in tables 2.3 to 2.10 is defined below. table 2.2 operation notation symbol description rd general register (destination) * 1 rs general register (source) * 1 rn general register * 1 ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register * 2 ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length notes: 1. general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 2. supported only by the h8s/2268 group.
section 2 cpu rev. 5.00 sep. 01, 2009 page 31 of 656 rej09b0071-0500 table 2.3 data transfer instructions instruction size * 1 function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in this lsi. movtpe b cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is iden tical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. ldm * 2 l @sp+ rn (register list) pops two or more general registers from the stack. stm * 2 l rn (register list) @?sp pushes two or more general registers onto the stack. notes: 1. refers to the operand size. b: byte w: word l: longword 2. only register er0 to er6 should be used when using the stm/ldm instruction.
section 2 cpu rev. 5.00 sep. 01, 2009 page 32 of 656 rej09b0071-0500 table 2.4 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 5.00 sep. 01, 2009 page 33 of 656 rej09b0071-0500 table 2.4 arithmetic operations instructions (2) instruction size * 1 function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register wi th data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas * 2 b @erd ? 0, 1 ( of @erd) tests memory contents, and sets the most significant bit (bit 7) to 1. notes: 1. refers to the operand size. b: byte w: word l: longword 2. only register er0, er1, er4, or er5 should be used when using the tas instruction.
section 2 cpu rev. 5.00 sep. 01, 2009 page 34 of 656 rej09b0071-0500 table 2.5 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. rotl rotr b/w/l rd (rotate) rd rotates general register contents. 1-bit or 2-bit rotations are possible. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 5.00 sep. 01, 2009 page 35 of 656 rej09b0071-0500 table 2.7 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 5.00 sep. 01, 2009 page 36 of 656 rej09b0071-0500 table 2.7 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 5.00 sep. 01, 2009 page 37 of 656 rej09b0071-0500 table 2.8 branch instructions instruction size function bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine
section 2 cpu rev. 5.00 sep. 01, 2009 page 38 of 656 rej09b0071-0500 table 2.9 system co ntrol instructions instruction size * 1 function trapa ? starts trap-instruction exception handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr, (eas) exr * 2 moves the source operand contents or immediate data to ccr or exr * 2 . although ccr and exr * 2 are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr (ead), exr * 2 (ead) transfers ccr or exr * 2 contents to a general register or memory. although ccr and exr * 2 are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr * 2 logically ands the ccr or exr * 2 contents with immediate data. orc b ccr #imm ccr, exr #imm exr * 2 logically ors the ccr or exr * 2 contents with immediate data. xorc b ccr #imm ccr, exr #imm exr * 2 logically xors the ccr or exr * 2 contents with immediate data. nop ? pc + 2 pc only increments the program counter. notes: 1. refers to the operand size. b: byte w: word 2. supported only by the h8s/2268 group.
section 2 cpu rev. 5.00 sep. 01, 2009 page 39 of 656 rej09b0071-0500 table 2.10 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+ r4l ? 1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+ r4 ? 1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction begins as soon as the transfer is completed. 2.6.2 basic instruction formats this lsi instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). figure 2.11 shows examples of instruction formats. ? operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers ar e specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. ? condition field specifies the branching condition of bcc instructions.
section 2 cpu rev. 5.00 sep. 01, 2009 page 40 of 656 rej09b0071-0500 op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. rn rm op ea(disp) op cc ea(disp) bra d:16, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.11 instruction formats (examples) 2.7 addressing modes and eff ective address calculation the h8s/2000 cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructi ons can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
section 2 cpu rev. 5.00 sep. 01, 2009 page 41 of 656 rej09b0071-0500 table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 2.7.1 register direct ? rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2.7.2 register indirect ? @ern the register field of the instruc tion code specifies an address re gister (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). 2.7.3 register indirect with displacement ? @(d:16, ern) or @(d:32, ern) a 16-bit or 32-bit displacement contained in the inst ruction is added to an address register (ern) specified by the register field of the instructio n, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added.
section 2 cpu rev. 5.00 sep. 01, 2009 page 42 of 656 rej09b0071-0500 2.7.4 register indirect with po st-increment or pre-decrement ? @ern+ or @-ern register indirect wi th post-increment ? @ern+: the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the addr ess register contents and the sum is stored in the address register. the value added is 1 for byte acce ss, 2 for word transfer instruction, or 4 for longword transfer instruction. for the word or longword transfer instructions, the register value should be even. register indirect wi th pre-decrement ? @-ern: the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register fi eld in the instruction code, and the result is the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transf er instruction, or 4 for longword transfer instruction. for the word or longword transfer instructions, the register value should be even. 2.7.5 absolute address ? @aa:8, @aa:16, @aa:24, or @aa:32 the instruction code contains th e absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). table 2.12 indicates the acce ssible absolute address ranges. to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, th e upper 24 bits are all a ssumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.12 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: * normal mode is not available in this lsi.
section 2 cpu rev. 5.00 sep. 01, 2009 page 43 of 656 rej09b0071-0500 2.7.6 immediate ? #xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 program-counter relative ? @(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instruc tions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the addre ss of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. 2.7.8 memory indirect ? @@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all a ssumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode * , h'000000 to h'0000ff in advanced mode). in normal mode, the memory operand is a word operand and the branch address is 16 bits long. in advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. if an odd address is specified in word or longwor d memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further informa tion, see section 2.5.2, memory data formats.) note: * normal mode is not available in this lsi.
section 2 cpu rev. 5.00 sep. 01, 2009 page 44 of 656 rej09b0071-0500 specified by @aa:8 specified by @aa:8 branch address branch address reserved (a) normal mode * (a) advanced mode note: * normal mode is not available in this lsi. figure 2.12 branch a ddress specification in memory indirect mode 2.7.9 effective address calculation table 2.13 indicates how effective addresses ar e calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
section 2 cpu rev. 5.00 sep. 01, 2009 page 45 of 656 rej09b0071-0500 table 2.13 effective a ddress calculation (1) no 1 offset 1 2 4 r op 31 0 31 23 2 3 register indirect with d isplacement @(d:16,ern) or @ (d:32,ern) 4 r op disp r op rm op rn 31 0 31 0 r op don't care 31 23 31 0 don't care 31 0 disp 31 0 31 0 31 23 31 0 don't care 31 23 31 0 don't care 24 24 24 24 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ ? register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand size byte word longword operand is general register contents.
section 2 cpu rev. 5.00 sep. 01, 2009 page 46 of 656 rej09b0071-0500 table 2.13 effective a ddress calculation (2) no 5 op 31 23 31 0 don't care abs @aa:8 7 h'ffff op 31 23 31 0 don't care @aa:16 op @aa:24 @aa:32 abs 15 16 31 23 31 0 don't care 31 23 31 0 don't care abs op abs 6 op imm #xx:8/#xx:16/#xx:32 8 24 24 24 24 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 31 23 7 program-counter relative @(d:8,pc) /@(d:16,pc) memory indirect @@aa:8 ? normal mode * ? advanced mode 31 0 don't care 23 0 disp 0 31 23 31 0 don't care disp op 23 op 8 abs 31 0 abs h'000000 7 8 0 15 31 23 31 0 don't care 15 h'00 16 op abs 31 0 abs h'000000 7 8 0 31 24 24 24 note: * normal mode is not available in this lsi. pc contents sign extension memory contents memory contents
section 2 cpu rev. 5.00 sep. 01, 2009 page 47 of 656 rej09b0071-0500 2.8 processing states the h8s/2000 cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and pow er-down state. figure 2. 13 indicates the state transitions. ? reset state in this state, the cpu and all on-chip peripheral modules are initialized and not operating. when the res input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset stat e. reset exception hand ling starts when the res signal changes from low to high. for details , refer to section 4, exception handling. the reset state can also be entered by a watchdog timer overflow. ? exception-handling state the exception-handling state is a transient state that occurs when the cp u alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. the cpu fetches a start address (vector) from th e exception vector table and branches to that address. for further details, refer to section 4, exception handling. ? program execution state in this state, the cpu executes pr ogram instructions in sequence. ? bus-released state (h8s/2268 group only) in a product which has a bus master other than the cpu, such as a data transfer controller (dtc), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. ? power-down state this is a power-down state in which the cpu stops operating. the program stop state occurs when a sleep instruction is executed or the cpu enters hardware standby mode. for further details, refer to section 22, power-down modes.
section 2 cpu rev. 5.00 sep. 01, 2009 page 48 of 656 rej09b0071-0500 exception handling state bus-released state * 4 hardware standby mode * 2 software standby mode reset state * 1 sleep mode power-down state * 3 program execution state end of bus request * 4 bus request * 4 interrupt request external interrupt request res = high request for ex ception handling stby = high, res = low end of bus request * 4 bus reque st * 4 slee p instruction, s s by = 0 sleep instruction, ssby = 1 notes: 1. 2. 3. 4. from any state except hardware standby mode, a transition to the reset state occurs whenever re s goes low. a transition can also be made to the reset state when the watchdog timer overflows. from any state, a transition to hardware standby mode occurs when stby goes low. apart from these states, there are also the watch mode, subactive mode, and the subsleep mode. see section 22, power-down modes. supported only by the h8s/2268 group. end of exception handling figure 2.13 state transitions
section 2 cpu rev. 5.00 sep. 01, 2009 page 49 of 656 rej09b0071-0500 2.9 usage notes 2.9.1 tas instruction only register er0, er1, er4, or er5 should be used when using the tas instruction. the tas instruction is not generated by the renesas h8s and h8/300 series c/c++ compilers. if the tas instruction is used as a user-defined intrinsic function, ensure that only register er0, er1, er4, or er5 is used. 2.9.2 stm/ldm instruction with the stm or ldm instruction, the er7 register is used as the stack pointer, and thus cannot be used as a register that allows save (stm) or restore (ldm) operation. with a single stm or ldm instruction, two to four registers can be saved or restored. the available registers are as follows: for two registers: er0 and er1, er2 and er3, or er4 and er5 for three registers: er0 to er2, or er4 to er6 for four registers: er0 to er3 for the renesas technology h8s or h8/300 series c/c++ compiler, the stm/ldm instruction including er7 is not created. 2.9.3 bit manipulation instructions when bit-manipulation is used with registers that include write-only bits, bits to be manipulated may not be manipulated properly or bits unrelat ed to the bit-manipulation may be changed. some values read from write-only bits are fixed and some are undefined. when such bits are the operands of bit-manipulation instructions that use read values in arithmetic operations (bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild), the desired bit-manipulation will not be executed. also, bit-manipulation instructions that write back data according to the results of arithmetic operations (bset, bclr, bnot, bst, bist) may change bits that are not related to the bit- manipulation. therefore, special care is necessary wh en using these instructions with registers that include write-only bits.
section 2 cpu rev. 5.00 sep. 01, 2009 page 50 of 656 rej09b0071-0500 the bset, bclr, bnot, bst and bist in structions are executed as follows: 1. data is read in bytes. 2. the operation corresponding to the instruction is applied to the specified bit of the data. 3. the byte produced by the bit-manipulation is written back. ? consider this example, where the bclr instruction is executed to clear only bit 4 in p1ddr of port 1. p1ddr is an 8-bit register that consists of write-only bits and specifies input or output for each pin of port 1. reading of these bits is not valid, since values read are specified as undefined. in the following example, the bclr instructi on specifies p14 as an input. before the operation, p17 to p14 are set as output pins and p13 to p10 are set as input pins. the value of p1ddr is h'f0. p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output output input input input input p1ddr 1 1 1 1 0 0 0 0 to switch p14 from an output to an input, the value of bit 4 in p1ddr has to be changed from 1 to 0 (h'f0 to h'e0). the bclr instruction us ed to clear bit 4 in p1ddr is as follows. bclr #4, @p1ddr however, the above bit-manipulation of the write-only p1ddr register may cause the following problem. the data in p1ddr is read in bytes. data read from p1ddr is undefined. thus, regardless of whether the value in the register is 0 or 1, it is impossible to tell which value will be read. all bits in p1ddr are write-only, thus read as unde fined. the actual value in p1ddr is h'f0. let us assume that the value read is h'f8, where the value of bit 3 is read as 1 rather than its actual value of 0. p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output output input input input input p1ddr 1 1 1 1 0 0 0 0 read value 1 1 1 1 1 0 0 0
section 2 cpu rev. 5.00 sep. 01, 2009 page 51 of 656 rej09b0071-0500 the target bit of the data read out is then mani pulated. in this example, clearing bit 4 of h'f8 leaves us with h'e8. p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output output input input input input p1ddr 1 1 1 1 0 0 0 0 after bit- manipulation 1 1 1 0 1 0 0 0 after the bit-manipulation, the data is then written back to p1ddr, and execution of the bclr instruction is complete. p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output input output input input input p1ddr 1 1 1 0 1 0 0 0 write value 1 1 1 0 1 0 0 0 this instruction was meant to change the value of p1ddr to h'e0, but h'e8 was written back instead. p13, which should be an input pin, has been turned into an output pin. note that while the error in this case occu rred because bit 3 in p1 ddr was read as 1, the values read from bits 7 to 0 in p1ddr are undefined. bit-manipulation instructions that write back values might change any bit from 0 to 1 or 1 to 0. section 2.9.4, access method for registers with write- only bits, describes a way to avoid this possibility when changing the values of registers that include write-only bits. the bclr instruction can be used to clear flags in the internal i/o registers to 0. in this case, if it is obvious that a given flag has been set to 1 because an interrupt handler has been entered, there is no need to read the flag . 2.9.4 access method for regist ers with write-only bits a read value from a write-only bit using a data-transfer or a bit-manipulation instruction is undefined. to avoid using the read value for subsequent operations, follow the procedure shown below to access registers that include write-only bits. when writing to registers that include write-only bits, set up a work area in memory such as on- chip ram, write the data to the work area, read the data back from the memory, and then write the data to the registers that include write-only bits.
section 2 cpu rev. 5.00 sep. 01, 2009 page 52 of 656 rej09b0071-0500 changing value of register including write-only bit writing initial value write initial data to work area copy data from work area to register including write-only bit access data in work area (data-transfer and bit-manipulation instructions can be used) copy data from work area to register including write-only bit figure 2.14 flowchart of access method for registers with write-only bits ? consider the following example, where onl y bit 4 in p1ddr of port 1 is cleared. p1ddr is an 8-bit register that consists of write-only bits and specifies input or output for each pin of port 1. reading of these bits is not valid, since values read are specified as undefined. in the following example, the bclr instruction specifies p14 as an input. start by writing the initial value h'f0, which will be written to p1ddr, to the work area (ram0) in memory. mov.b #h'f0, r0l mov.b r0l, @ram0 mov.b r0l, @p1ddr p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output output input input input input p1ddr 1 1 1 1 0 0 0 0 ram0 1 1 1 1 0 0 0 0 p14 is now an output. to switch p14 from an output to an input, the value of bit 4 in p1ddr has to be changed from 1 to 0 (h'f0 to h'e0). clear bit 4 of ram0 using the bclr instruction. bclr #4, @ram0
section 2 cpu rev. 5.00 sep. 01, 2009 page 53 of 656 rej09b0071-0500 p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output output input input input input p1ddr 1 1 1 1 0 0 0 0 ram0 1 1 1 0 0 0 0 0 ram locations are readable and writable, so there is no possibility of a problem if a bit- manipulation instruction is used to clear only bit 4 of ram0. read the value from ram0 and then write it back to p1ddr. mov.b @ram0, r0l mov.b r0l, @p1ddr p17 p16 p15 p14 p13 p12 p11 p10 i/o output output output input input input input input p1ddr 1 1 1 0 0 0 0 0 ram0 1 1 1 0 0 0 0 0 following this procedure in access to registers that include write-only bits makes the behavior of the program independent of the type of instruction.
section 2 cpu rev. 5.00 sep. 01, 2009 page 54 of 656 rej09b0071-0500
section 3 mcu operating modes rev. 5.00 sep. 01, 2009 page 55 of 656 rej09b0071-0500 section 3 mcu operating modes 3.1 operating mode selection this lsi supports the advanced single-chip mode. the operating mode is determined by the setting of the mode pins (md2 and md1). only mode 7 can be used in this lsi. therefore, all mode pins must be fixed high. do not change the mode pin settings during operation. table 3.1 mcu operating mode selection external data bus mcu operating mode md2 md1 cpu operating mode description on-chip rom initial width max. width 7 1 1 advanced mode single-chip mode enabled ? ?
section 3 mcu operating modes rev. 5.00 sep. 01, 2009 page 56 of 656 rej09b0071-0500 3.2 register description the following register is related to the operating mode. ? mode control register (mdcr) 3.2.1 mode control register (mdcr) mdcr monitors the current operating mode. bit bit name initial value r/w descriptions 7 ? 1 r/w reserved this bit is always read as 1 and cannot be modified. 6 to 3 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 2 1 mds2 mds1 ? ? r r mode select 2 and 1 these bits indicate the input levels at pins md2 and md1 (the current operating mode). bits mds2 and mds1 correspond to md2 and md1, respectively. mds2 and mds1 are read-only bits and they cannot be written to. the mode pin (md2 and md1) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. these latches are canceled by a reset. 0 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 3.3 operating mode the cpu can access a 16-mbyte address space in ad vanced mode. on-chip rom is valid and the external address cannot be used.
section 3 mcu operating modes rev. 5.00 sep. 01, 2009 page 57 of 656 rej09b0071-0500 3.4 address map figure 3.1 shows the address map in each operating mode. h'000000 h'ffb000 h'03ffff h'000000 h'01ffff h'ffd000 h'ffefbf h'ffefbf h'fff800 h'fff800 h'ffff3f h'ffff3f h'ffff60 h'ffff60 h'ffffc0 h'ffffc0 h'ffffff h'ffffff h8s/2268 h8s/2266 rom: 128 kbytes, ram: 8 kbytes mode 7 advanced single-chip mode on-chip ram on-chip ram on-chip ram internal i/o registers internal i/o registers rom: 256 kbytes, ram: 16 kbytes mode 7 advanced single-chip mode on-chip ram on-chip ram on-chip ram internal i/o registers internal i/o registers figure 3.1 address map (1)
section 3 mcu operating modes rev. 5.00 sep. 01, 2009 page 58 of 656 rej09b0071-0500 h'00ffff h'000000 h'ffe800 h'ffefbf h'fff800 h'ffff3f h'ffff60 h'ffffc0 h'ffffff h8s/2262 rom: 64 kbytes, ram: 2 kbytes mode 7 advanced single-chip mode on-chip ram on-chip ram on-chip ram internal i/o registers internal i/o registers h'01ffff h'000000 h'ffe000 h'ffefbf h'fff800 h'ffff3f h'ffff60 h'ffffc0 h'ffffff h8s/2265 and h8s/2264 rom: 128 kbytes, ram: 4 kbytes mode 7 advanced single-chip mode on-chip ram on-chip ram on-chip ram internal i/o registers internal i/o registers figure 3.1 address map (2)
section 4 exception handling rev. 5.00 sep. 01, 2009 page 59 of 656 rej09b0071-0500 section 4 exception handling 4.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, trace * , trap instruction, or interrupt. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exception handling requests are accepted at all times in program execution state. exception sources, the stack structure, and operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits in syscr. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. the cpu enters the reset state when the res pin is low. trace * starts when execution of the current instruction or exception handling ends, if the trace (t) bit in the exr is set to 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. low trap instruction started by execution of a trap instruction (trapa). trap instruction exception handling requests are accepted at all times in program execution state. note: * supported only by the h8s/2268 group.
section 4 exception handling rev. 5.00 sep. 01, 2009 page 60 of 656 rej09b0071-0500 4.2 exception sources and exception vector table different vector addresses are assigned to differe nt exception sources. table 4.2 lists the exception sources and their vector addresses. table 4.2 exception handling vector table exception source vector number vector address advanced mode * 1 reset 0 h'0000 to h'0003 reserved for system use 1 h'0004 to h'0007 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 trace * 4 5 h'0014 to h'0017 direct transitions * 3 6 h'0018 to h'001b external interrupt (nmi) 7 h'001c to h'001f trap instruction (four sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f reserved for system use 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b 15 h'003c to h'003f external interrupt irq0 16 h'0040 to h'0043 irq1 17 h'0044 to h'0047 reserved for system use 18 h'0048 to h'004b external interrupt irq3 19 h'004c to h'004f irq4 20 h'0050 to h'0053 irq5 * 4 21 h'0054 to h'0057 reserved for system use 22 h'0058 to h'005b 23 h'005c to h'005f
section 4 exception handling rev. 5.00 sep. 01, 2009 page 61 of 656 rej09b0071-0500 exception source vector number vector address advanced mode * 1 internal interrupt * 2 24 ? 107 h'0060 to h'0063 ? h'01ac to h'01af external interrupt wkp0 to wkp7 108 h'01b0 to h'01b3 internal interrupt 120 ? 123 h'01e0 to h'01e3 ? h'01ec to h'01ef notes: 1. lower 16 bits of the address. 2. for details of internal interrupt vectors, see section 5.4.3, interrupt exception handling vector table. 3. for details on direct transitions, see section 22.10, direct transitions. 4. supported only by the h8s/2268 group. 4.3 reset a reset has the highest exception priority. when the res pin goes low, all processing halts and this lsi enters the reset. a reset initializes the internal state of the cpu and the registers of on-chip peripheral modules. the interrupt control mode is 0 immediately after reset. when the res pin goes high from the low state, this lsi starts reset exception handling. the chip can also be reset by overflow of the watchdog timer. for details see section 12, watchdog timer (wdt). 4.3.1 reset exception handling when the res pin goes low, this lsi enters the reset. to ensure that this lsi is reset, hold the res pin low for at least 20 ms at power-up. to reset the chip during operation, hold the res pin low for at least 20 states. when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows. 1. the internal state of the cpu and the regi sters of the on-chip peripheral modules are initialized, the t bit in exr * is cleared to 0, and the i bits in exr * and ccr is set to 1. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the ad dress indicated by the pc. note: * supported only by the h8s/2268 group.
section 4 exception handling rev. 5.00 sep. 01, 2009 page 62 of 656 rej09b0071-0500 figures 4.1 shows an example of the reset sequence. res high vector fetch internal processing prefetch of first program instruction (1)(3) reset exception handling vector address(when reset, (1)=h'000000, (3)=h'000002) (2)(4) start address (contents of reset exception handling vector address) (5) start address ((5)=(2)(4)) (6) first program instruction internal address bus internal read signal internal write signal internal data bus (1) (2) (4) (6) (3) (5) figure 4.1 reset sequence (advanced mode with on-chip rom enabled) 4.3.2 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immedi ately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: sp). 4.3.3 state of on-chip peripheral modules after reset release after reset release, mstpcra is initialized to h'3f, mstpcrb to mstpcrd are initialized to h'ff, and all modules except the dtc (only for the h8s/2268 group) enter module stop mode. consequently, on-chip peripheral module registers cannot be read or written to. register reading and writing is enabled when the module stop mode is exited.
section 4 exception handling rev. 5.00 sep. 01, 2009 page 63 of 656 rej09b0071-0500 4.4 traces (supported only by the h8s/2268 group) traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trac e mode, a trace exception occurs on completion of each instruction. trace mode is not affected by interrupt masking. table 4.3 shows the state of ccr and exr after execution of trace exception handling. trace mode is canceled by clearing the t bit in exr to 0. interrupts are accepted even w ithin the trace exception handling routine. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by th e rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. table 4.3 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 2 1 ? ? 0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution 4.5 interrupts interrupts are controlled by the interrupt controller. the interrupt controller of the h8s/2268 group has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. for details, refer to section 5, interrupt controller. interrupt exception handling is conducted as follows: 1. the values in the program counter (pc), condition code register (ccr), and extended control register (exr) * are saved to the stack. 2. the interrupt mask bit is updated and the t bit * is cleared to 0.
section 4 exception handling rev. 5.00 sep. 01, 2009 page 64 of 656 rej09b0071-0500 3. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and program execution begins from that address. note: * supported only by the h8s/2268 group. 4.6 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at a ll times in the program execution state. trap instruction exception handling is conducted as follows: 1. the values in the program counter (pc), condition code register (ccr), and extended control register (exr) * are saved to the stack. 2. the interrupt mask bit is updated and the t bit * is cleared. 3. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and prog ram execution starts from that address. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4.4 shows the status of ccr and exr * after execution of trap instruction exception handling. table 4.4 status of ccr and exr * after trap instruct ion exception handling ccr exr * interrupt control mode i ui i2 to i0 t 0 1 ? ? ? 2 * 1 ? ? 0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution note: * supported only by the h8s/2268 group.
section 4 exception handling rev. 5.00 sep. 01, 2009 page 65 of 656 rej09b0071-0500 4.7 stack status after exception handling figures 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. ccr pc (24 bit) sp note: 1. ignored on return 2. supported only by the h8s/2268 group. exr reserved * 1 pc (24 bit) sp interrupt control mode 0 interrupt control mode * 2 figure 4.2 stack status after exception handling (advanced mode) 4.8 usage note when accessing word data or longword data, this lsi assumes that the lowest address bit is 0. the stack should always be accessed by word transfer in struction or longword transfer instruction, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.3 shows an example of what happens when the sp value is odd.
section 4 exception handling rev. 5.00 sep. 01, 2009 page 66 of 656 rej09b0071-0500 sp h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff r1l pc sp ccr pc sp ccr: pc: r1l: sp: condition code register program counter general register r1l stack pointer trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost legend: note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. figure 4.3 operation when sp value is odd
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 67 of 656 rej09b0071-0500 section 5 interrupt controller 5.1 features this lsi controls interrupts with the interrupt controller. the interrupt controller has the following features: ? two interrupt control modes (h8s/2268 group only) ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with ipr (h8s/2268 group only) ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources except wkp7 to wkp0 are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? external interrupts h8s/2268 group: 14 (nmi, irq5 to irq3, irq1, irq0, and wkp7 to wkp0) h8s/2264 group: 13 (nmi, irq4, irq3, irq1, irq0, and wkp7 to wkp0) ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. falling edge, ri sing edge, or both edge detection, or level sensing, can be independently selected for irq5 to irq3, irq1, and irq0. wkp7 to wkp0 are accepted at a falling edge ? dtc control (h8s/2268 group only) ? the dtc can be activated by an interrupt request. a block diagram of the interrupt controller for the h8s/2268 group is shown in figure 5.1, and that for the h8s/2264 group is shown in figure 5.2
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 68 of 656 rej09b0071-0500 syscr nmi input irq input internal interrupt request swdtend to tei2 nmieg intm1, intm0 nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu iscr: ier: isr: ienr1: iwpr: ipr: syscr: irq sense control register irq enable register irq status register interrupt enable register1 wakeup interrupt request register interrupt priority register system control register legend: ienr1 wkp input wkp input unit iwpr figure 5.1 block diagram of interrupt controller for h8s/2268 group
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 69 of 656 rej09b0071-0500 syscr nmi input irq input internal interrupt request wovi0 to tei2 nmieg intm1, intm0 nmi input unit irq input unit isr iscr ier interrupt controller priority determination interrupt request vector number i ccr cpu iscr: ier: isr: ienr1: iwpr: syscr: irq sense control register irq enable register irq status register interrupt enable register1 wakeup interrupt request register system control register legend: ienr1 wkp input wkp input unit iwpr figure 5.2 block diagram of interrupt controller for h8s/2264 group
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 70 of 656 rej09b0071-0500 5.2 input/output pins table 5.1 summarizes the pins of the interrupt controller. table 5.1 pin configuration name i/o function nmi input nonmaskable external interrupt rising or falling edge can be selected irq5 * irq4 irq3 irq2 irq1 irq0 input input input input input input maskable external interrupts rising, falling, or both edges, or level sensing, can be selected wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 input input input input input input input input maskable external interrupts accepted at a falling edge note: * supported only by the h8s/2268 group.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 71 of 656 rej09b0071-0500 5.3 register descriptions the interrupt controller has the following registers. system control register (syscr) irq sense control register h (iscrh) irq sense control register l (iscrl) irq enable register (ier) irq status register (isr) interrupt priority register a (ipra) * interrupt priority register b (iprb) * interrupt priority register c (iprc) * ? interrupt priority register d (iprd) * ? interrupt priority register e (ipre) * ? interrupt priority register f (iprf) * ? interrupt priority register g (iprg) * ? interrupt priority register i (ipri) * ? interrupt priority register j (iprj) * ? interrupt priority register k (iprk) * ? interrupt priority register l (iprl) * ? interrupt priority register m (iprm) * ? interrupt priority register o (ipro) * ? wakeup interrupt request register (iwpr) ? interrupt enable register 1 (ienr1) note: * supported only by the h8s/2268 group. 5.3.1 system control register (syscr) syscr selects the interrupt control mode and the detected edge for nmi.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 72 of 656 rej09b0071-0500 bit bit name initial value r/w descriptions 7 ? 0 r/w reserved the write value should always be 0. 6 ? 0 ? reserved this bit is always read as 0, and cannot be modified. 5 4 intm1 intm0 0 0 r/w r/w interrupt control mode 1 and 0 h8s/2268 group: these bits select the control mode of the interrupt controller. 00: interrupt control mode 0 (interrupts are controlled by the i bit.) 01: setting prohibited 10: interrupt control mode 2 (interrupts are controlled by the i2 to i0 bits and ipr.) 11: setting prohibited h8s/2264 group: the write value should always be 0. 00: interrupt control mode 0 (interrupts are controlled by the i bit.) 01: setting prohibited 10: setting prohibited 11: setting prohibited 3 nmieg 0 r/w nmi edge select selects the valid edge of the nmi interrupt input. 0: an interrupt is requested at the falling edge of nmi input 1: an interrupt is requested at the rising edge of nmi input 2 ? 0 r/w reserved the write value should always be 0. 1 ? 0 ? reserved this bit is always read as 0, and cannot be modified. 0 ? 1 r/w reserved the write value should always be 0.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 73 of 656 rej09b0071-0500 5.3.2 interrupt priority registers a to g, i to m, and o (ipra to iprg, ipri to iprm, ipro) (h8s/2268 group only) the ipr registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between interrupt sources and ipr settings is shown in table 5.2. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0, and cannot be modified. 6 5 4 ipr6 ipr5 ipr4 1 1 1 r/w r/w r/w sets the priority of the corresponding interrupt source 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 3 ? 0 ? reserved this bit is always read as 0, and cannot be modified. 2 1 0 ipr2 ipr1 ipr0 1 1 1 r/w r/w r/w sets the priority of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest)
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 74 of 656 rej09b0071-0500 5.3.3 irq enable register (ier) ier controls the enabling and disabling of interrupt requests irqn (h8s/2268 group: n = 5 to 3, 1, 0; h8s/2264 group: n = 4, 3, 1, 0). bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved the write value should always be 0. 5 irq5e 0 r/w h8s/2268 group: irq5 enable the irq5 interrupt request is enabled when this bit is 1. h8s/2264 group: reserved the write value should always be 0. 4 irq4e 0 r/w irq4 enable the irq4 interrupt request is enabled when this bit is 1. 3 irq3e 0 r/w irq3 enable the irq3 interrupt request is enabled when this bit is 1. 2 ? 0 r/w reserved the write value should always be 0. 1 irq1e 0 r/w irq1 enable the irq1 interrupt request is enabled when this bit is 1. 0 irq0e 0 r/w irq0 enable the irq0 interrupt request is enabled when this bit is 1.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 75 of 656 rej09b0071-0500 5.3.4 irq sense control registers h and l (iscrh and iscrl) the iscr registers select the source that generates an interrupt request at pins irqn (h8s/2268 group: n = 5 to 3, 1, 0; h8s/2264 group: n = 4, 3, 1, 0). specifiable sources are the falling edge, rising edge, or both edge detection, and level sensing. bit bit name initial value r/w description 15 to 12 ? all 0 r/w reserved the write value should always be 0. 11 10 irq5scb irq5sca 0 0 r/w r/w h8s/2268 group: irq5 sense control b irq5 sense control a 00: interrupt request generated at irq5 input level low 01: interrupt request generated at falling edge of irq5 input 10: interrupt request generated at rising edge of irq5 input 11: interrupt request generated at both falling and rising edges of irq5 input h8s/2264 group: reserved the write value should always be 0. 9 8 irq4scb irq4sca 0 0 r/w r/w irq4 sense control b irq4 sense control a 00: interrupt request generated at irq4 input level low 01: interrupt request generated at falling edge of irq4 input 10: interrupt request generated at rising edge of irq4 input 11: interrupt request generated at both falling and rising edges of irq4 input
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 76 of 656 rej09b0071-0500 bit bit name initial value r/w description 7 6 irq3scb irq3sca 0 0 r/w r/w irq3 sense control b irq3 sense control a 00: interrupt request generated at irq3 input level low 01: interrupt request generated at falling edge of irq3 input 10: interrupt request generated at rising edge of irq3 input 11: interrupt request generated at both falling and rising edges of irq3 input 5, 4 ? all 0 r/w reserved the write value should always be 0. 3 2 irq1scb irq1sca 0 0 r/w r/w irq1 sense control b irq1 sense control a 00: interrupt request generated at irq1 input level low 01: interrupt request generated at falling edge of irq1 input 10: interrupt request generated at rising edge of irq1 input 11: interrupt request generated at both falling and rising edges of irq1 input 1 0 irq0scb irq0sca 0 0 r/w r/w irq0 sense control b irq0 sense control a 00: interrupt request generated at irq0 input level low 01: interrupt request generated at falling edge of irq0 input 10: interrupt request generated at rising edge of irq0 input 11: interrupt request generated at both falling and rising edges of irq0 input
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 77 of 656 rej09b0071-0500 5.3.5 irq status register (isr) isr indicates the status of irqn (h8s/2268 group: n = 5 to 3, 1, 0; h8s/2264 group: n = 4, 3, 1, 0) interrupt requests. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved the write value should always be 0. 5 irq5f 0 r/(w) * 1 h8s/2268 group: irq5 flag indicates the status of an irq5 interrupt request. [setting condition] when the interrupt source selected by the iscr registers occurs [clearing conditions] ? cleared by reading irq5f flag when irq5f = 1, then writing 0 to irq5f flag ? when interrupt exception handling is executed when low-level detection is set and irq5 input is high level ? when irq5 interrupt exception handling is executed when falling, rising, or both-edge detection is set ? when the dtc is activated by an irq5 interrupt, and the disel bit in mrb of the dtc is cleared to 0 h8s/2264 group: reserved the write value should always be 0.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 78 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 3 irq4f irq3f 0 0 r/(w) * 2 r/(w) * 2 irq4 and irq3 flags indicate the status of irq4 and irq3 interrupt requests. [setting condition] when the interrupt source selected by the iscr registers occurs [clearing conditions] ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 (h8s/2268 group only) 2 ? 0 r/w reserved the write value should always be 0.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 79 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 0 irq1f irq0f 0 0 r/(w) * 2 r/(w) * 2 irq1 and irq0 flags indicate the status of irq1 and irq0 interrupt requests. [setting condition] when the interrupt source selected by the iscr registers occurs [clearing conditions] ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 (h8s/2268 group only) notes: 1. in the h8s/2268 group, only 0 can be written to this bit to clear the flag. in the h8s/2264 group, this bit is readable/writable. 2. only 0 can be written to this bit to clear the flag.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 80 of 656 rej09b0071-0500 5.3.6 wakeup interrupt request register (iwpr) iwpr indicates the status of wk p7 to wkp0 interrupt requests. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * wakeup interrupt request flags indicate the status of wkp7 to wkp0 interrupt requests. [setting condition] when wkp7 to wkp0 pins are set as wakeup inputs and these pins have a falling edge. [clearing condition] when this bit reads 1 and then write 0. note: only 0 can be written to this bit to clear the flag. 5.3.7 interrupt enable register 1 (ienr1) ienr1 enables/disables wakeup interrupt requests. bit bit name initial value r/w description 7 ienwp 0 r/w wakeup interrupt enable enables/disables wkp7 to wkp0 interrupt requests 0: wkp7 to wkp0 pin interrupt requests are disabled. 1: wkp7 to wkp0 pin interrupt requests are enabled. 6 to 1 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 0 ? 0 r/w reserved this bit should always be 0 when it is read.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 81 of 656 rej09b0071-0500 5.4 interrupt sources 5.4.1 external interrupts there are 14 external interrupts for the h8s/2268 group: nmi, irq5 to irq3, irq1, irq0, and wkp7 to wkp0, and 13 external interrupts for the h8s/2264 group: nmi, irq4, irq3, irq1, irq0, and wkp7 to wkp0. these interrupts can be used to restore this lsi from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. irqn interrupts (h8s/2268 group: n = 5 to 3, 1, and 0; h8s/2264 group: n = 4, 3, 1, and 0): irqn interrupts are requested by an input signal at irqn pins. irqn interrupts have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at irqn pins. ? enabling or disabling of irqn interrupt requests can be selected with ier. ? the interrupt priority level can be set with ipr. (h8s/2268 group only) ? the status of irqn interrupt requests is indicat ed in isr. isr flags can be cleared to 0 by software. a block diagram of irqn interrupts is shown in figure 5.3. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: h8s/2268 group: n = 5 to 3, 1, 0 h8s/2264 group: n = 4, 3, 1, 0 figure 5.3 block diagram of irqn interrupts
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 82 of 656 rej09b0071-0500 the set timing for irqnf is shown in figure 5.4. irqn input pin irqnf note: h8s/2268 group: n = 5 to 3, 1, 0 h8s/2264 group: n = 4, 3, 1, 0 figure 5.4 set timing for irqnf the detection of irqn interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0; and use the pin as an i/o pin for another function. irqnf interrupt request flag is set to 1 when the setting condition is satisfied, regardless of ier settings. accordingly, refer to only necessary flags. wkp7 to wkp0 interrupts: wkp7 to wkp0 interrupts are requested by falling edge input signal at wkp7 to wkp0 pins. wkp7 to wkp0 interrupts have the following features: ? wpcr selects whether the pjn/ wkpn /segn+1 pin is used as the pjn pin or wkpn pin when the pjn/ wkpn /segn+1 pin is not used as the segn+1 pin. (n = 7 to 0) for pin switching, see 9.8.5 wakeup control register (wpcr). ? ienr1 can be used to select enabling or disabling of wkp7 to wkp0 interrupt requests. ? ipr sets the interrupt priority level. (h8s/2268 group only) ? iwpr indicates the status of wk p7 to wkp0 interrupt requests. iwpr flag can be cleared to 0 by software. the block diagram of interrupts wkp7 to wkp0 is shown in figure 5.5.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 83 of 656 rej09b0071-0500 wkp7 to wkp0 iwpf7 ienwp s r q iwpf6 s r q iwpf0 s r q wkp0 input - - - - - - - - - - - - - - - - - - - - clear signal falling edge detection circuit falling edge detection circuit falling edge detection circuit interrupt request w kp6 input wkp7 input figure 5.5 block diagram of interrupts wkp7 to wkp0 figure 5.6 shows the iwpfn setting timing. wkpn input iwpfn (n = 7 to 0) figure 5.6 iwpfn setting timing the vector number for the wkp7 to wkp0 interrupt exception handling is 108. eight interrupt pins are assigned to one vector number. accordingly, determine the source using an exception handling routine. the detection of interrupts wkp7 to wkp0 does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 84 of 656 rej09b0071-0500 the corresponding ddr to 0; and use the pin as an i/o pin for another function. irqnf interrupt request flag is set to 1 when the setting condition is satisfied, regardless of ier settings. accordingly, refer to only necessary flags. 5.4.2 internal interrupts for each on-chip peripheral module, there are flags that indicate th e interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. 5.4.3 interrupt exception handling vector table table 5.2 shows interrupt exception handling sources , vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by m eans of the ipr. (h8s/2268 group only) modules set at the same priority will conform to their default priorities. priorities within a module are fixed.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 85 of 656 rej09b0071-0500 table 5.2 interrupt sources, vector addresses, and interrupt priorities vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr * 2 * 3 priority nmi 7 h'001c high external pin irq0 16 h'0040 ipra6 to ipra4 irq1 17 h'0044 ipra2 to ipra0 reserved 18 h'0048 iprb6 to iprb4 irq3 19 h'004c irq4 20 h'0050 iprb2 to iprb0 irq5 * 3 21 h'0054 reserved 22 23 h'0058 h'005c iprc6 to iprc4 dtc * 3 swdtend (completion of software initiation data transfer) 24 h'0060 iprc2 to iprc0 watchdog timer 0 wovi0 (interval timer 0) 25 h'0064 iprd6 to iprd4 pc break * 3 pc break 27 h'006c ipre6 to ipre4 a/d adi (completion of a/d conversion) 28 h'0070 ipre2 to ipre0 watchdog timer 1 wovi1 (interval timer 1) 29 h'0074 ? reserved 30 31 h'0078 h'007c tpu channel 0 * 3 tgi0a (tgr0a input capture/compare-match) 32 h'0080 iprf6 to iprf4 tgi0b (tgr0b input capture/compare-match) 33 h'0084 tgi0c (tgr0c input capture/compare-match) 34 h'0088 tgi0d (tgr0d input capture/compare- match) 35 h'008c tci0v (overflow 0) 36 h'0090 ? reserved 37 38 39 h'0094 h'0098 h'009c low
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 86 of 656 rej09b0071-0500 vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr * 2 * 3 priority tpu channel 1 tgi1a (tgr1a input capture/compare-match) 40 h'00a0 iprf2 to iprf0 high tgi1b (tgr1b input capture/compare-match) 41 h'00a4 tci1v (overflow 1) 42 h'00a8 tci1u (underflow 1) * 3 43 h'00ac tpu channel 2 tgi2a (tgr2a input capture/compare-match) 44 h'00b0 iprg6 to iprg4 tgi2b (tgr2b input capture/compare-match) 45 h'00b4 tci2v (overflow 2) 46 h'00b8 tci2u (underflow 2) * 3 47 h'00bc 8-bit timer channel 0 cmia0 (compare-match a0) 64 h'0100 ipri6 to ipri4 cmib0 (compare-match b0) 65 h'0104 ovi0 (overflow 0) 66 h'0108 ? reserved 67 h'010c 8-bit timer channel 1 cmia1 (compare-match a1) 68 h'0110 ipri2 to ipri0 cmib1 (compare-match b1) 69 h'0114 ovi1 (overflow 1) 70 h'0118 ? reserved 71 h'011c eri0 (receive error 0) 80 h'0140 iprj2 to iprj0 rxi0 (receive completion 0) 81 h'0144 sci channel 0 txi0 (transmit data empty 0) 82 h'0148 tei0 (transmit end 0) 83 h'014c low
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 87 of 656 rej09b0071-0500 vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr * 2 * 3 priority eri1 (receive error 1) 84 h'0150 iprk6 to iprk4 high sci channel 1 rxi1 (receive completion 1) 85 h'0154 txi1 (transmit data empty 1) 86 h'0158 tei1 (transmit end 1) 87 h'015c 8-bit timer channel 2 * 3 cmia2 (compare-match a2) 92 h'0170 iprl6 to iprl4 cmib2 (compare-match b2) 93 h'0174 ovi2 (overflow 2) 94 h'0178 ? reserved 95 h'017c 8-bit timer channel 3 * 3 cmia3 (compare-match a3) 96 h'0180 cmib3 (compare-match b3) 97 h'0184 ovi3 (overflow 3) 98 h'0188 ? reserved 99 h'018c iic channel 0 * 4 iici0 (1-byte transmission/ reception completion) 100 h'0190 reserved 101 h'0194 iprl2 to iprl0 iici1 (1-byte transmission/ reception completion) 102 h'0198 iic channel 1 * 3 reserved 103 h'019c ovi4 (overflow 4) 104 h'01a0 ovi5 (overflow 5) 105 h'01a4 ovi6 (overflow 6) 106 h'01a8 8-bit reload timer channels 4 to 7 * 3 ovi7 (overflow 7) 107 h'01ac iprm6 to iprm4 external pins wkp7 to wkp0 108 h'01b0 iprm2 to iprm0 low
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 88 of 656 rej09b0071-0500 vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr * 2 * 3 priority eri2 (receive error 2) 120 h'01e0 ipro6 to ipro4 high rxi2 (receive completion 2) 121 h'01e4 sci channel 2 txi2 (transmit data empty 2) 122 h'01e8 tei2 (transmit end 2) 123 h'01ec low notes: 1. lower 16 bits of the start address. 2. ipr6 to ipr4, and ipr2 to ipr0 bits are reserved, because these bits have no corresponding interruption. these bits are always read as 0 and cannot be modified. 3. supported only by the h8s/2268 group. 4. supported as an option by h8s/2264 group. 5.5 operation 5.5.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2268 differ depending on the interrupt control mode. nmi interrupts are accepted at all tim es except in the reset state and the hardware standby state. in the case of irq interrupts, wkp interrupts and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5.3 shows the interrupt control modes. the interrupt controller performs interrupt control according to th e interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in ipr * , and the masking state indicated by the i bit in the cpu?s ccr, and bits i2 to i0 in exr * . note: * supported only by the h8s/2268 group.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 89 of 656 rej09b0071-0500 table 5.3 interrupt control modes syscr interrupt control mode intm1 intm0 priority setting registers * interrupt mask bits description 0 0 0 ? i interrupt mask control is performed by the i bit. ? 1 ? ? setting prohibited 2 * 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. ? 1 ? ? setting prohibited note: * supported only by the h8s/2268 group. figures 5.7 and 5.8 show block diagrams of the priority decision circuits for the h8s/2268 group and h8s/2264 group, respectively. interrupt acceptance control 8-level mask control default priority determination vector number interrupt control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 5.7 block diagram of interrupt control operation for h8s/2268 group
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 90 of 656 rej09b0071-0500 interrupt acceptance control default priority determination vector number interrupt source interrupt control mode 0 i figure 5.8 block diagram of interrupt control operation for h8s/2264 group interrupt acceptance control: in interrupt control mode 0, in terrupt acceptance is controlled by the i bit in ccr. table 5.4 shows the interrupts select ed in each interrupt control mode. table 5.4 interrupts selected in each interrupt control mode (1) interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * x all interrupts legend: x: don't care note: * supported only by the h8s/2268 group. 8-level control (h8s/2268 group only): in interrupt control mode 2, 8-level mask level determination is performed for the selected inte rrupts in interrupt accepta nce control according to the interrupt priority level (ipr). the interrupt source selected is the interrupt with the highest priority level, and whose priority level set in ipr is higher than the mask level. table 5.5 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0).
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 91 of 656 rej09b0071-0500 default priority determination: when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated (h8s/2268 group only). interrupt sources with a lower priority than the accep ted interrupt source are held pending. table 5.6 shows operations and control signal functions in each interrupt control mode. table 5.6 operations and control signal functions in each interrupt control mode setting interrupt acceptance control 8-level control * 3 interrupt control mode intm1 intm0 i i2 to i0 * 3 ipr * 3 default priority determination t (trace) 0 0 0 o im x ? ? * 2 o ? 2 * 3 1 0 x ? * 1 o im pr o t legend: o : interrupt operation control performed x: no operation. (all interrupts enabled) im: used as interrupt mask bit pr: sets priority. ? : not used. notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting. 3. supported only by the h8s/2268 group.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 92 of 656 rej09b0071-0500 5.5.2 interrupt control mode 0 enabling and disabling of irq interrupts, wkp interrupts and on-chip peripheral module interrupts can be set by means of the i bit in the cpu?s ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5.9 shows a flowchart of the inte rrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. if the i bit is cleared, an interrupt request is accepted. 3. interrupt requests are sent to the interrupt c ontroller, the highest-ranked interrupt according to the priority system is accepted, and ot her interrupt requests are held pending. 4. when the cpu accepts an interrupt request , it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruc tion to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except nmi. 7. the cpu generates a vector address for th e accepted interrupt and st arts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 93 of 656 rej09b0071-0500 yes program execution status interrupt generated nmi irq1 irq0 save pc and ccr i=1 read vector address branch to interrupt handling routine hold pending tei2 yes yes no yes yes yes no no no i=0 no figure 5.9 flowchart of proce dure up to interrupt acceptance in interrupt control mode 0
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 94 of 656 rej09b0071-0500 5.5.3 interrupt control mode 2 (h8s/2268 group only) eight-level masking is implemented for irq interrupts, wkp interrupts and on-chip peripheral module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 5.10 shows a flowchart of the in terrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. when the cpu accepts an interrupt request , it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the in terrupt mask level is set to h'7. 7. the cpu generates a vector address for th e accepted interrupt and st arts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 95 of 656 rej09b0071-0500 yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5.10 flowchart of procedure up to interrupt acceptance in control mode 2 5.5.4 interrupt exception handling sequence figure 5.11 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advan ced mode, and the program area and stack area are in on-chip memory.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 96 of 656 rej09b0071-0500 (14) (12) (10) (6) (4) (2) (1) (5) (7) ( 9 ) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10)(12)) first instruction of interrupt handling routine (6) (8) ( 9 ) (11) (10) (12) (13) (14) (8) figure 5.11 interrupt exception handling
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 97 of 656 rej09b0071-0500 5.5.5 interrupt response times this lsi is capable of fast wo rd transfer to on-chip memory, has the program area in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 5.7 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5.7 are explained in table 5.8. table 5.7 interrupt response times (states) normal mode * 5 advanced mode no. execution status intm1 = 0 intm1 = 1 intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 3 3 3 3 2 number of wait states until executing instruction ends * 2 1 to 19 + 2s i 1 to 19 + 2s i 1 to 19 + 2s i 1 to 19 + 2s i 3 pc, ccr, exr stack save 2s k 3s k 2s k 3s k 4 vector fetch s i s i 2s i 2s i 5 instruction fetch * 3 2s i 2s i 2s i 2s i 6 internal processing * 4 2 2 2 2 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. 5. not available in this lsi.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 98 of 656 rej09b0071-0500 table 5.8 number of states in interru pt handling routine execution status object of access external device * 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i branch address read s j 1 4 6 + 2 m 2 3 + m stack manipulation s k legend: m: number of wait states in an external device access. note: * cannot be used in this lsi. 5.5.6 dtc activation by int errupt (h8s/2268 group only) the dtc can be activated by an in terrupt. in this case, the following selections can be made. 1. interrupt request to cpu 2. activation request to dtc 3. multiple selection of 1 and 2 above. for details on interrupt request, which enables dtc activation, see section 8, data transfer controller (dtc). figure 5.12 shows a block diagram of dtc and interrupt controller.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 99 of 656 rej09b0071-0500 dtcer selection circuit selection signal clear signal dtvecr dtc cpu irq interrupt interrupt request interrupt source clear signal swdte clear signal cpu interrupt request vector number dtc activation request vector number on-chip peripheral module control logic priority determination clear signal i, i2 to i0 interrupt controller figure 5.12 dtc and interrupt controller interrupt controller of dtc control has the following three main functions. interrupt source selection: for interruption source, select dtc activation request or cpu interruption request by the dtce bits in dtcera to dtcerf, and dtceri of the dtc. after dtc data transfer, the dtce bit is cleared to 0, and an interrupt request to the cpu can be made by the setting of the disel bit in mrb of the dtc. when dtc performs data transfer for prescribed number of times and transfer counter becomes 0, the dtce bit should be cleared to 0 and an interrupt request to the cpu is made after dtc data transfer. priority determination: dtc activation source is selected according to priority of default setting. mask level and priority level do not affect the selection. for details, see section 8.4, location of register information and dtc vector table. operation order: when the same interrupts are select ed as dtc activation source and cpu interruption source, dtc data is transferred, and then cpu interrupt exception processing is made. table 5.9 shows interrupt source selection and interrupt source clear control by the setting of the dtce bit in dtcera to dtcerf, and dtceri of the dtc and the setting of the disel bit in mrb of the dtc.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 100 of 656 rej09b0071-0500 table 5.9 interrupt source se lection and cl ear control settings dtc interrupt source selection and clear control dtce desel dtc cpu 0 * x # 1 0 # x 1 o # legend: # : corresponding interrupt is used. interrupt source is cleared. (the cpu should clear the source flag in the interrupt processing routine.) o: corresponding interrupt is used. interrupt source is not cleared. x: corresponding interrupt cannot be used. * : don?t care usage note: interrupt sources of the sci and a/d conve rter are cleared when the dtc reads or writes prescribed register, and they do not depend on the dtce or disel bit. 5.6 usage notes 5.6.1 contention between interru pt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction su ch as bclr or mov, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an inte rrupt source flag is cleared to 0. figure 5.13 shows an example in which the cmiea bit in the tcr register of the 8-bit timer is cleared to 0. the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 101 of 656 rej09b0071-0500 internal address bus internal write signal cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5.13 contention between interrupt generation and disabling 5.6.2 instructions that disable interrupts the instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions are executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.6.3 when interrupts are disabled there are times when interr upt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt accep tance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction.
section 5 interrupt controller rev. 5.00 sep. 01, 2009 page 102 of 656 rej09b0071-0500 5.6.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 5.6.5 irq interrupt when operating by clock input, acceptance of input to an irq is synchronized with the clock. in software standby mode and watch mode, the input is accepted asynchronously. for details on the input conditions, see section 25.2.3 , 25.3.3, control signal timing. 5.6.6 nmi interrupt usage notes the nmi interrupt is part of the exception processing performed cooperatively by the lsi?s internal interrupt controller and the cpu when the system is operating normally under the specified electrical cond itions. no operations, including nmi interrupts, are guaranteed when operation is not normal (runaway status) due to software problems or abnormal input to the lsi?s pins. in such cases, the lsi may be restored to the normal program execution state by applying an external reset.
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 103 of 656 rej09b0071-0500 section 6 pc break controller (pbc) the h8s/2268 group includes a pc break controller (pbc), while the h8s/2264 group does not. the pc break controller (pbc) provides functions that simplify program debugging. using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. a block diagram of the pc break controller is shown in figure 6.1. 6.1 features ? two break channels (a and b) ? 24-bit break address ? bit masking possible ? four types of break compare conditions ? instruction fetch ? data read ? data write ? data read/write ? bus master ? either cpu or cpu/dtc can be selected ? the timing of pc break exception handling after the occurrence of a break condition is as follows: ? immediately before execution of the instruction fetched at the set address (instruction fetch) ? immediately after execution of the instruction that accesses data at the set address (data access) ? module stop mode can be set pbc0000b_000020020700
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 104 of 656 rej09b0071-0500 output control output control mask control pc break interrupt match signal mask control bara bcra barb bcrb comparator control logic comparator control logic internal address access status match signal figure 6.1 block diagram of pc break controller 6.2 register descriptions the pc break controller has the following registers. ? break address register a (bara) ? break address register b (barb) ? break control register a (bcra) ? break control register b (bcrb) 6.2.1 break address register a (bara) bara is a 32-bit readable/writable register that specifies the channel a break address. bit bit name initial value r/w description 31 to 24 ? undefined ? reserved these bits are read as an undefined value and cannot be modified. 23 to 0 baa23 to baa0 h'000000 r/w these bits set the channel a pc break address.
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 105 of 656 rej09b0071-0500 6.2.2 break address register b (barb) barb is the channel b break address register. the bit configuration is the same as for bara. 6.2.3 break control register a (bcra) bcra controls channel a pc breaks. bit bit name initial value r/w description 7 cmfa 0 r/(w) * 1 condition match flag a [setting condition] when a condition set for channel a is satisfied [clearing condition] when 0 is written to cmfa after reading * 2 cmfa = 1 6 cda 0 r/w cpu cycle/dtc cycle select a selects the channel a break condition bus master. 0: cpu 1: cpu or dtc 5 4 3 bamra2 bamra1 bamra0 0 0 0 r/w r/w r/w break address mask register a2 to a0 these bits specify which bits of the break address set in bara are to be masked. 000: baa23 ? 0 (all bits are unmasked) 001: baa23 ? 1 (lowest bit is masked) 010: baa23 ? 2 (lower 2 bits are masked) 011: baa23 ? 3 (lower 3 bits are masked) 100: baa23 ? 4 (lower 4 bits are masked) 101: baa23 ? 8 (lower 8 bits are masked) 110: baa23 ? 12 (lower 12 bits are masked) 111: baa23 ? 16 (lower 16 bits are masked) 2 1 csela1 csela0 0 0 r/w r/w break condition select selects break condition of channel a. 00: instruction fetch is used as break condition 01: data read cycle is used as break condition 10: data write cycle is used as break condition 11: data read/write cycle is used as break condition
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 106 of 656 rej09b0071-0500 bit bit name initial value r/w description 0 biea 0 r/w break interrupt enable when this bit is 1, the pc break interrupt request of channel a is enabled. notes: 1. only a 0 can be written to this bit to clear the flag. 2. read the state wherein cmfa = 1 twice or more, when the cmfa is polled after inhibiting the pc break interruption. 6.2.4 break control register b (bcrb) bcrb is the channel b break control register. the bit configuration is the same as for bcra. 6.3 operation the operation flow from break condition setting to pc break interrupt exception handling is shown in section 6.3.1, pc break interrupt due to instruction fetch, and 6.3.2, pc break interrupt due to data access, taking the example of channel a. 6.3.1 pc break interrupt due to instruction fetch 1. set the break address in bara. for a pc break caused by an instruction fetch, set the address of the first instruction byte as the break address. 2. set the break conditions in bcr. set bit 6 (cda) to 0 to select the cpu because the bus master mu st be the cpu for a pc break caused by an instruction fetch. set the address bits to be masked to bits 3 to 5 (bama2 to 0). set bits 1 and 2 (csela1 to 0) to 00 to specify an instruction fetch as the break condition. set bit 0 (biea) to 1 to enable break interrupts. 3. when the instruction at the set address is fetc hed, a pc break request is generated immediately before execution of the fetched instruction, and the condition match flag (cmfa) is set. 4. after priority determination by the interrupt controller, pc break interrupt exception handling is started.
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 107 of 656 rej09b0071-0500 6.3.2 pc break interrupt due to data access 1. set the break address in bara. for a pc break caused by a data access, set the ta rget rom, ram, i/o, or external address space address as the break address. stack operati ons and branch address reads are included in data accesses. 2. set the break conditions in bcra. select the bus master with bit 6 (cda). set the address bits to be masked to bits 3 to 5 (bama2 to 0). set bits 1 and 2 (csela1 to 0) to 01, 10, or 11 to specify data access as the break condition. set bit 0 (biea) to 1 to enable break interrupts. 3. after execution of the instruction that perfor ms a data access on the set address, a pc break request is generated and the condition match flag (cmfa) is set. 4. after priority determination by the interrupt controller, pc break interrupt exception handling is started. 6.3.3 notes on pc break interrupt handling ? when a pc break interrupt is generated at the transfer address of an eepmov.b instruction pc break exception handling is ex ecuted after all data transfers have been completed and the eepmov.b instruction has ended. ? when a pc break interrupt is generated at a dtc transfer address pc break exception handling is executed after the dtc has completed the specified number of data transfers, or after data for which the disel bit is set to 1 has been transferred. 6.3.4 operation in transitions to power-down modes the operation when a pc break interrupt is set for an instruction fetch at the address after a sleep instruction is shown below. ? when the sleep instruction ca uses a transition fr om high-speed (medium-speed) mode to sleep mode: after execution of the sleep instru ction, a transition is not made to sleep mode, and pc break interrupt handling is executed. after execution of pc break interrupt handling, the instruction at the address after the sleep instru ction is executed (figure 6.2 (a)). ? when the sleep instruction ca uses a transition fr om high speed mode to subactive mode (figure 6.2 (b)). ? when the sleep instruction caus es a transition from subactive mode to high speed (medium speed) mode (figure 6.2 (c)). ? when the sleep instruction causes a transiti on to software standby mode or watch mode:
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 108 of 656 rej09b0071-0500 after execution of the sleep inst ruction, a transition is made to the respective mode, and pc break interrupt handling is not executed. however, the cmfa or cmfb flag is set (figure 6.2 (d)). sleep instruction execution high-speed (medium-speed) mode sleep instruction execution subactive mode system clock subclock direct transition exception handling pc break exception handling execution of instruction after sleep instruction subclock system clock, oscillation settling time sleep instruction execution transition to respective mode direct transition exception handling pc break exception handling execution of instruction after sleep instruction pc break exception handling execution of instruction after sleep instruction (a) (b) (c) (d) sleep instruction execution figure 6.2 operation in power-down mode transitions 6.3.5 when instruction executi on is delayed by one state while the break interrupt enable bit is set to 1, instruction execution is one state later than usual. ? for 1-word branch instructions (bcc d:8, bsr, jsr, jmp, trapa, rte, and rts) in on-chip rom or ram. ? when break interruption by instruction fetch is set, the set address indicates on-chip rom or ram space, and that address is used for data access, the instruction th at executes the data access is one state later than in normal operation. ? when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip rom or ram, the instruction will be one state later than in normal operation. addressing modes: @ern, @(d:16,ern), @(d:32,ern), @-ern/ern+, @aa:8, @aa:24, @aa:32, @(d:8,pc), @(d:16,pc), @@aa:8 ? when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the se t instruction is nop or sleep, or has #xx, rn as its addressing mode, and that instruction is located in on-chip rom or ram, the instruction will be one state later than in normal operation.
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 109 of 656 rej09b0071-0500 6.4 usage notes 6.4.1 module stop mode setting pbc operation can be disabled or enabled usi ng the module stop control register. the initial setting is for pbc operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 22, power-down modes. 6.4.2 pc break interrupts the pc break interrupt is shared by channels a and b. the channel from which the request was issued must be determined by the interrupt handler. 6.4.3 cmfa and cmfb the cmfa and cmfb flags are not automatically cleared to 0, so 0 must be written to cmfa or cmfb after first reading the flag while it is set to 1. if the flag is left set to 1, another interrupt will be requested after interrupt handling ends. 6.4.4 pc break interrupt when dtc is bus master a pc break interrupt generated wh en the dtc is the bus master is accepted after the bus has been transferred to the cpu by the bus controller. 6.4.5 pc break set for instruction fetch at address following bsr, jsr, jmp, trapa, rte, or rts instruction when a pc break is set for an in struction fetch at an address following a bsr, jsr, jmp, trapa, rte, or rts instruction: even if the instruction at the address follo wing a bsr, jsr, jmp, trapa, rte, or rts instruction is fetched, it is not executed, and so a pc break interrupt is not generated by the instruction fetch at the next address.
section 6 pc break controller (pbc) rev. 5.00 sep. 01, 2009 page 110 of 656 rej09b0071-0500 6.4.6 i bit set by ldc, andc, orc, or xorc instruction when the i bit is set by an ldc, andc, orc, or xorc instruction, a pc break interrupt becomes valid two states after the end of the executing instruction. if a pc break interrupt is set for the instruction following one of these instructions, since interrupts, including nmi, are disabled for a 3-state period in the case of ld c, andc, orc, and xor, the next instruction is always executed. for details, see section 5, interrupt controller. 6.4.7 pc break set for instruction fetc h at address following bcc instruction when a pc break is set for an instruction fetch at an address following a bcc instruction: a pc break interrupt is generate d if the instruction at the next address is executed in accordance with the branch condition, and is not generated if the instruction at the next address is not executed. 6.4.8 pc break set for instruction fetch at branch destination address of bcc instruction when a pc break is set for an instruction fetch at the branch destination address of a bcc instruction: a pc break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, and is not generated if the instruction at the branch destination is not executed.
section 7 bus controller rev. 5.00 sep. 01, 2009 page 111 of 656 rej09b0071-0500 section 7 bus controller the h8s/2000 cpu is driven by a system clock, denoted by the symbol . the bus controller controls a memory cycle and a bus cycle. different methods are used to access on-chip memory and on-chip peripheral modules. in the h8s/2268 group, the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu and data transfer controller (dtc). 7.1 basic timing the period from one rising edge of to the next is referred to as a "state". the memory cycle or bus cycle consists of one, two, or four stat es. different methods are used to access on-chip memory, on-chip peripheral modules, and the external address space. 7.1.1 on-chip memory access timing (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 7.1 shows the on-chip memory access cycle. t1 internal address bus bus cycle address read data write data internal read signal internal data bus internal write signal internal data bus read access write access figure 7.1 on-chip memory access cycle
section 7 bus controller rev. 5.00 sep. 01, 2009 page 112 of 656 rej09b0071-0500 7.1.2 on-chip peripheral module access timing (h'fffdac to h'ffffbf) addresses h'fffdac to h'ffffbf in the on-chip peripheral modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. for details, refer to section 24, list of registers. figure 7.2 shows access timing for the on-chip peripheral modules (h'fffdac to h'ffffbf). t1 t2 internal address bus bus cycle address read data write data internal read signal internal data bus internal write signal internal data bus read access write access figure 7.2 on-chip peripheral modul e access cycle (h'fffdac to h'ffffbf) 7.1.3 on-chip peripheral module access timing (h'fffc30 to h'fffca3) addresses h'fffc30 to h'fffca3 on the on-chip peripheral modules and registers are accessed in four states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. for details, refer to sec tion 24, list of register s. figure 7.3 shows access timing for the on-chip peripheral modules (h'fffc30 to h'fffca3). the on-chip module of which address is between h'fffc30 to h'fffca3 includes lcd, dtmf * , tmr4 * , ports h to l and ports m * and n * . the registers are wkp register and module stop control register d. note: * supported only by the h8s/2268 group.
section 7 bus controller rev. 5.00 sep. 01, 2009 page 113 of 656 rej09b0071-0500 internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t1 address read access write access t3 t2 t4 read data write data figure 7.3 on-chip peripheral modul e access cycle (h'fffc30 to h'fffca3) 7.2 bus arbitration (h8s/2268 group only) the bus controller has a bus arbiter th at arbitrates bus master operations. there are two bus masters, the cpu and dtc, which perform read/write operations when they control the bus. 7.2.1 order of priority of the bus masters each bus master requests the bus by means of a bus request signal. the bus arbiter detects the bus masters? bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low)
section 7 bus controller rev. 5.00 sep. 01, 2009 page 114 of 656 rej09b0071-0500 7.2.2 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. the cpu is the lowest-priority bus ma ster, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cy cles. however, if a bus cycle is executed in discrete operations, as in the case of a longwor d-size access, the bus is not transferred between such operations. for details, refer to section 2.7, bus states during instruction execution, in the h8s/2600 series, h8s/2000 series programming manual. ? if the cpu is in sleep mode, it transfers the bus immediately. the dtc sends the bus arbiter a request for the bus when an activation request is generated. 7.2.3 resets and the bus controller in a reset, the h8s/2268, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 115 of 656 rej09b0071-0500 section 8 data transfer controller (dtc) the h8s/2268 group includes a data transfer controller (dtc), while the h8s/2264 group does not. the dtc can be activated by an inte rrupt or software, to transfer data. figure 8.1 shows a block diagram of the dtc. the dtc?s register information is stored in th e on-chip ram. when the dtc is used, the rame bit in syscr must be set to 1. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. 8.1 features ? transfer is possible over any number of channels ? three transfer modes ? normal, repeat, and block transfer modes are available ? one activation source can trigger a number of data transfers (chain transfer) ? the direct specification of 16 -mbyte address space is possible ? activation by software is possible ? transfer can be set in byte or word units ? a cpu interrupt can be requested for the interrupt that activated the dtc ? module stop mode can be set dtch808b_000020020700
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 116 of 656 rej09b0071-0500 internal address bus dtcer a to dtcerf and dtceri interrupt controller interrupt request dtc on-chip ram internal data bus cpu interrupt request mra mrb cra crb dar sar mra, mrb: cra, crb: sar: dar: dtcera to dtcerf and dtceri: dtvecr: dtc mode registers a and b dtc transfer count registers a and b dtc source address register dtc destination address register dtc enable registers a to f and i dtc vector register legend: dtc service request control logic register information dtvecr figure 8.1 block diagram of dtc 8.2 register descriptions the dtc has the following registers. ? dtc mode register a (mra) ? dtc mode register b (mrb) ? dtc source address register (sar) ? dtc destination address register (dar) ? dtc transfer count register a (cra) ? dtc transfer count register b (crb) these six registers cannot be directly accessed from the cpu.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 117 of 656 rej09b0071-0500 when activated, the dtc reads a set of register information that is stored in on-chip ram to the corresponding dtc registers and transfers data. after the data transfer, it writes a set of updated register information back to the ram. ? dtc enable registers (dtcer) ? dtc vector register (dtvecr) 8.2.1 dtc mode register a (mra) mra selects the dtc operating mode. bit bit name initial value r/w description 7 6 sm1 sm0 undefined undefined ? ? source address mode 1 and 0 these bits specify an sar operation after a data transfer. 0x: sar is fixed 10: sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 11: sar is decremented after a transfer (by ?1 when sz = 0; by ?2 when sz = 1) 5 4 dm1 dm0 undefined undefined ? ? destination address mode 1 and 0 these bits specify a dar operation after a data transfer. 0x: dar is fixed 10: dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 11: dar is decremented after a transfer (by ?1 when sz = 0; by ?2 when sz = 1) 3 2 md1 md0 undefined undefined ? ? dtc mode 1 and 0 these bits specify the dtc transfer mode. 00: normal mode 01: repeat mode 10: block transfer mode 11: setting prohibited
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 118 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 dts undefined ? dtc transfer mode select specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: destination side is repeat area or block area 1: source side is repeat area or block area 0 sz undefined ? dtc data transfer size specifies the size of data to be transferred. 0: byte-size transfer 1: word-size transfer legend: x: don?t care 8.2.2 dtc mode register b (mrb) mrb is an 8-bit register that selects the dtc operating mode. bit bit name initial value r/w description 7 chne undefined ? dtc chain transfer enable this bit specifies a chain transfer. for details, refer to 8.5.4, chain transfer. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer, are not performed. 0: dtc data transfer completed (waiting for start) 1: dtc data transfer (reads new register information and transfers data) 6 disel undefined ? dtc interrupt select this bit specifies whether cpu interrupt is disabled or enabled after a data transfer. 0: interrupt request is issued to the cpu when the specified data transfer is completed. 1: dtc issues interrupt request to the cpu in every data transfer (dtc does not clear the interrupt request flag that is a cause of the activation).
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 119 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 to 0 ? undefined ? reserved these bits have no effect on dtc operation. the write value should always be 0. 8.2.3 dtc source address register (sar) sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 8.2.4 dtc destination address register (dar) dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 8.2.5 dtc transfer count register a (cra) cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). in repeat mode, crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). in block transfer mode, crah holds the block size while cral functions as an 8-bit block size counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated. 8.2.6 dtc transfer count register b (crb) crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transf er ends when the count reaches h'0000.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 120 of 656 rej09b0071-0500 8.2.7 dtc enable register (dtcer) dtcer is comprised of seven registers; dtcera to dtcerf and dtceri, and is a register that specifies dtc activation interrupt sources. the correspondence between interrupt sources and dtce bits is shown in table 8.1. for dtce bit setting, use bit manipulation instructions such as bset and bclr for reading and writing. if all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w dtc activation enable setting this bit to 1 specifies a relevant interrupt source as a dtc activation source. [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended ? these bits are not cleared when the disel bit is 0 and the specified number of transfers have not been completed
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 121 of 656 rej09b0071-0500 8.2.8 dtc vector register (dtvecr) dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. bit bit name initial value r/w description 7 swdte 0 r/w dtc software activation enable setting this bit to 1 activates dtc. only a 1 can be written to this bit. [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 s written to the disel bit after a software- activated data transfer end interrupt (swdtend) request has been sent to the cpu. ? when the disel bit is 1 and data transfer has ended, the specified number of transfers have ended, or software-activated data transfer is in process, this bit will not be cleared. 6 5 4 3 2 1 0 dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w dtc software activation vectors 0 to 6 these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + (vector number 2). for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420. these bits are writable when swdte=0.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 122 of 656 rej09b0071-0500 8.3 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. at the end of a data transfer (or the last c onsecutive transfer in the cas e of chain transfer), the activation source or corresponding dtcer bit is cleared. table 8.1 shows the relationship between the activation source and dtcer clearing. the activation source flag, in the case of rxi0, for example, is th e rdrf flag in sci_0. since there are a number of dtc activation sources , transferring the last byte (or word) does not clear the flag of its activation source. take appropriate steps at each interrupt processing. when an interrupt has been designated a dtc activation source, the existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. table 8.1 activation sou rce and dtcer clearing activation source the disel bit is 0, and transfer counts specified have not ended the disel bit is 1, or transfer counts specified have ended software activation ? the swdte bit is cleared to 0 ? the swdte bit retains 1 ? the interrupt request is sent to the cpu interrupt activation ? the corresponding dtcer bit retains 1 ? the activation source flag is cleared to 0 ? the corresponding dtcer bit is cleared to 0 ? the activation source flag retains 1 ? the interrupt request which becomes an activation source is sent to the cpu figure 8.2 shows a block diagram of activation source control. for details, see section 5, interrupt controller.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 123 of 656 rej09b0071-0500 cpu dtc dtcer source flag cleared on-chip peripheral module irq interrupt interrupt request clear clear controller clear request interrupt controller selection circuit interrupt mask select dtvecr figure 8.2 block diagram of dtc activation source control 8.4 location of register info rmation and dtc vector table locate the register informatio n in the on-chip ram (addresses: h'ffebc0 to h'ffefbf). register information should be located at an address that is a multiple of four within the range. locating the register information in address space is shown in figure 8.3. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information. in the case of chain transfer, register information should be located in consecutive areas as shown in figure 8.3, and the register information start address should be located at the vector address corresponding to the interrupt source. figure 8.4 shows the correspondence between dtc vector address and register information. the dtc reads th e start address of the register information from the vector address set for each activation source, a nd then reads the register information from that start address. when the dtc is activated by software, th e vector address is obtained from: h'0400 + (dtvecr[6:0] 2). for example, if dtvecr is h'10, the vector address is h'0420. the configuration of the vector address is the same in both normal * and advanced modes, a 2-byte unit being used in both cases. these two bytes specify the lower bits of the register information start address. note: * normal mode cannot be used in this lsi.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 124 of 656 rej09b0071-0500 mra 0123 sar mrb dar cra crb mra sar mrb dar cra crb lower address 4 bytes register information register information for 2nd transfer in chain transfer register information start address chain transfer figure 8.3 the location of dtc register information in address space register information start address register information chain transfer dtc vector address figure 8.4 correspondence between dtc v ector address and register information
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 125 of 656 rej09b0071-0500 table 8.2 interrupt sources, dtc vect or addresses, and corresponding dtces interrupt source origin of interrupt source vector number dtc vector address dtce * priority software write to dtvecr dtvecr h'0400 + vector number 2 ? high external pin irq0 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 a/d adi (a/d conversion end) 28 h'0438 dtceb6 tgi0a 32 h'0440 dtceb5 tpu channel 0 tgi0b 33 h'0442 dtceb4 tgi0c 34 h'0444 dtceb3 tgi0d 35 h'0446 dtceb2 tgi1a 40 h'0450 dtceb1 tpu channel 1 tgi1b 41 h'0452 dtceb0 tgi2a 44 h'0458 dtcec7 tpu channel 2 tgi2b 45 h'045a dtcec6 cmia0 64 h'0480 dtced3 8-bit timer channel 0 cmib0 65 h'0482 dtced2 cmia1 68 h'0488 dtced1 8-bit timer channel 1 cmib1 69 h'048a dtced0 rxi0 81 h'04a2 dtcee3 sci channel 0 txi0 82 h'04a4 dtcee2 rxi1 85 h'04aa dtcee1 sci channel 1 txi1 86 h'04ac dtcee0 cmia2 92 h'04b8 dtcef5 8-bit timer channel 2 cmib2 93 h'04ba dtcef4 cmia3 96 h'04c0 dtcef3 8-bit timer channel 3 cmib3 97 h'04c2 dtcef2 low
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 126 of 656 rej09b0071-0500 interrupt source origin of interrupt source vector number dtc vector address dtce * priority iic channel 0 iici0 100 h'04c8 dtcef1 high iic channel 1 iici1 102 h'04cc dtcef0 rxi2 121 h'04f2 dtcei7 sci channel 2 txi2 122 h'04f4 dtcei6 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. 8.5 operation register information is stored in on-chip ram. when activated, the dtc reads register information in on-chip ram and transfers data. after the data transfer, the dtc writes updated register information back to the memory. the pre-storage of register information in memory makes it possible to transfer data over any required number of channels. the transfer mode can be specified as normal, repeat, and block transfer mode. setting the chne bit in mrb to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). the 24-bit sar designates the dtc transfer source address, and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed depending on its register information. figure 8.5 shows the flowchart of dtc operation.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 127 of 656 rej09b0071-0500 start end read dtc vector read register infomation data transfer write register information interupt exception handling * clear dtcer clear an activeation flag note: * for details, see section related to each peripheral module. chne = 1 next transfer yes yes no transfer counter = 0 or disel = 1 no figure 8.5 flowchart of dtc operation 8.5.1 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have been completed, a cpu interrupt can be requested. table 8.3 lists the register information in normal mode. figure 8.6 shows the memory mapping in normal mode.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 128 of 656 rej09b0071-0500 table 8.3 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register b crb not used sar dar transfer figure 8.6 memory mapping in normal mode 8.5.2 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 8.4 lists the register information in repeat mode. figure 8.7 shows the memory mapping in repeat mode.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 129 of 656 rej09b0071-0500 table 8.4 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count dtc transfer count register b crb not used sar or dar dar or sar repeat area transfer figure 8.7 memory mapping in repeat mode 8.5.3 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is designated as a block area. the block size can be between 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register speci fied as the block area is restored. the other address register is then incremente d, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have been completed, a cpu interrupt is requested. table 8.5 lists the register information in block transfer mode. figure 8.8 shows the memory mapping in block transfer mode.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 130 of 656 rej09b0071-0500 table 8.5 register information in block transfer mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register b crb transfer count first block transfer block area nth block dar or sar sar or dar figure 8.8 memory mapping in block transfer mode
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 131 of 656 rej09b0071-0500 8.5.4 chain transfer setting the chne bit in mrb to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 8.9 shows the memory map for chain transfer. when activated, the dtc r eads the register information start addr ess stored at the vector address, and then reads the first register in formation at that start address. after the data transfer, the chne bit will be tested. when it has been set to 1, dtc reads the next register information located in a consecutive area and performs the data transfer. these sequences are repeated until the chne bit is cleared to 0. in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected. dtc vector address register information chne=1 register information chne=0 register information start address source destination source destination figure 8.9 chain transfer operation
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 132 of 656 rej09b0071-0500 8.5.5 interrupts an interrupt request is issued to the cpu when the dtc has completed the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of software activation, a software-ac tivated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine will then clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 8.5.6 operation timing figures 8.10 to 8.12 show the dtc operation timings. dtc activation request dtc request address vector read read write data transfer transfer information write transfer information read figure 8.10 dtc operation timing (example in normal mode or repeat mode)
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 133 of 656 rej09b0071-0500 dtc activation request dtc request address vector read read write read write data transfer transfer information write transfer information read figure 8.11 dtc operation timing (example of block transfer mode, with block size of 2) dtc activation request dtc request address vector read read write read write data transfer data transfer transfer information write transfer information write transfer information read transfer information read figure 8.12 dtc operation timing (example of chain transfer)
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 134 of 656 rej09b0071-0500 8.5.7 number of dtc execution states table 8.6 lists execution status for a single dtc data transfer, and table 8.7 shows the number of states required for eac h execution status. table 8.6 dtc execution status mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 legend: n: block size (initial setting of crah and cral) table 8.7 number of states requi red for each execution status object to be accessed on- chip ram on- chip rom internal i/o registers external devices * bus width 32 16 8 16 8 16 access states 1 1 2 2 2 3 2 3 vector read s i ? 1 ? ? 4 6 + 2 m 2 3 + m register information read/write s j 1 ? ? ? ? ? ? ? byte data read s k 1 1 2 2 2 3 + m 2 3 + m word data read s k 1 1 4 2 4 6 + 2 m 2 3 + m byte data write s l 1 1 2 2 2 3 + m 2 3 + m word data write s l 1 1 4 2 4 6 + 2 m 2 3 + m execution status internal operation s m 1 legend: m: the number of wait states for accessing external devices. note: * cannot be used in this lsi. the number of execution states is calculated from using the formula below. note that is the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1).
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 135 of 656 rej09b0071-0500 number of execution states = i s i + (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in the on-chip rom, normal mode is set, and data is transferred from on-chip rom to an internal i/o register, then the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states. 8.6 procedures for using dtc 8.6.1 activation by interrupt the procedure for using the dtc with interrupt activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in on-chip ram. 2. set the start address of the register in formation in the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. 5. after one data transfer has been completed, or after the specified number of data transfers have been completed, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. 8.6.2 activation by software the procedure for using the dtc with software activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in on-chip ram. 2. set the start address of the register in formation in the dtc vector address. 3. check that the swdte bit is 0. 4. write 1 to swdte bit and the vector number to dtvecr. 5. check the vector number written to dtvecr. 6. after one data transfer has been completed, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have been completed, the swdte bit is held at 1 and a cpu interrupt is requested.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 136 of 656 rej09b0071-0500 8.7 examples of use of dtc 8.7.1 normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. 1. set mra to a fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. 2. set the start address of the register in formation at the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the sci to the appropriate receive mode. se t the rie bit in scr to 1 to enable the reception complete (rxi) interr upt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cp u should be enabled to accept receive error interrupts. 5. each time the reception of one byte of data has been completed on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generate d, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automa tically cleared to 0. 6. when cra becomes 0 after the 128 data transfer s have been completed, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine will perform wrap-up processing. 8.7.2 software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. 1. set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. 2. set the start address of the register inform ation at the dtc vector address (h'04c0). 3. check that the swdte bit in dtvecr is 0. ch eck that there is curr ently no transfer activated by software.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 137 of 656 rej09b0071-0500 4. write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. 5. read dtvecr again and check that it is set to th e vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer , go back to step 3. 6. if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. 7. after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing. 8.8 usage notes 8.8.1 module stop mode setting dtc operation can be disabled or enabled usi ng the module stop control register. the initial setting is for dtc operation to be enabled. register access is disabled by setting module stop mode. module stop mode cannot be set during dt c operation. for details, refer to section 22, power-down modes. 8.8.2 on-chip ram the mra, mrb, sar, dar, cra, and crb regist ers are all located in on-chip ram. when the dtc bit is used, the rame bit in syscr should not be cleared to 0. 8.8.3 dtce bit setting for dtce bit setting, use bit manipulation instruc tions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
section 8 data transfer controller (dtc) rev. 5.00 sep. 01, 2009 page 138 of 656 rej09b0071-0500
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 139 of 656 rej09b0071-0500 section 9 i/o ports the h8s/2268 group has ten i/o ports (ports 1, 3, 7, f, h, and j to n), and two input-only port (ports 4 and 9). the h8s/2264 group has eight i/o ports (ports 1, 3, 7, f, h, and j to l), and two input-only port (ports 4 and 9). table 9.1 summarizes the port func tions. the pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) used to read the pin states. the input-only ports do not have ddr and dr registers. port j has a built-in input pull-up mos function and an input pull-up mos control register (pcr) to control the on/off state of input pull-up mos. port 3 includes an open-drain control register (odr) that controls the on/off state of the output buffer pmos. all the i/o ports can drive a single ttl load and a 30 pf capacitive load. the p34 and p35 pins on port 3 are nmos push pull outputs. pins irq and wkp are schmitt-trigger inputs. pins ph0 to ph3 and ports j to n in the h8s/2268 group and pins ph0 to ph3 and ports j to l in the h8s/2264 group are shared as lcd segment pins and common pins. they can be selected on an 8-bit basis.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 140 of 656 rej09b0071-0500 table 9.1 h8s/2268 group port functions (1) port description port and other functions name input/output and output type port 1 p17/tiocb2/tclkd p16/tioca2/ irq1 schmitt trigger input ( irq1 , irq0 ) p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb p12/tiocc0/tclka p11/tiocb0 general i/o port also functioning as tpu i/o pins and interrupt input pins p10/tioca0 port 3 p35/sck1/scl0/ irq5 p34/rxd1/sda0 p33/txd1/sda0 p32/sck0/sda1/ irq4 p31/rxd0 general i/o port also functioning as sci_0 and sci_1 i/o pins, i 2 c bus interface i/o pins, and interrupt input pins p30/txd0 specifiable of open drain output schmitt trigger input ( irq5 , irq4 ) nmos push-pull output (p35, p34, sck1) port 4 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 general input port also functioning as a/d converter analog input pins p40/an0 port 7 p77/txd2 p76/rxd2 p75/tmo3/sck2 p74/tmo2 p73/tmo1 p72/tmo0 general i/o port also functioning as sci_2 i/o pins and 8-bit timer i/o pins p71/tmri23/tmci23 p70/tmri01/tmci01
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 141 of 656 rej09b0071-0500 port description port and other functions name input/output and output type port 9 p97/an9/da1 general input port also functioning as a/d converter analog input and d/a converter analog output pins p96/an8/da0 port f general i/o port also functioning as interrupt input pins and an a/d converter input pins pf3/ adtrg / irq3 schmitt trigger input ( irq3 ) port h general input port ph7 ph3/com4 ph2/com3 ph1/com2 general i/o port also functioning as lcd common output pins ph0/com1 port j pj7/ wkp7 /seg8 pj6/ wkp6 /seg7 pj5/ wkp5 /seg6 pj4/ wkp4 /seg5 built-in input pull-up mos schmitt trigger input ( wkp7 to wkp0 ) pj3/ wkp3 /seg4 pj2/ wkp2 /seg3 pj1/ wkp1 /seg2 general i/o port also functioning as wakeup input pins and lcd segment output pins pj0/ wkp0 /seg1 port k pk7/seg16 pk6/seg15 pk5/seg14 pk4/seg13 pk3/seg12 pk2/seg11 general i/o port also functioning as lcd segment output pins pk1/seg10 pk0/seg9
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 142 of 656 rej09b0071-0500 port description port and other functions name input/output and output type port l pl7/seg24 pl6/seg23 pl5/seg22 pl4/seg21 pl3/seg20 pl2/seg19 pl1/seg18 general i/o port also functioning as lcd segment output pins pl0/seg17 port m pm7/seg32 pm6/seg31 pm5/seg30 pm4/seg29 pm3/seg28 pm2/seg27 pm1/seg26 general i/o port also functioning as lcd segment output pins pm0/seg25 port n pn7/seg40 pn6/seg39 pn5/seg38 pn4/seg37 pn3/seg36 pn2/seg35 general i/o port also functioning as lcd segment output pins pn1/seg34 pn0/seg33
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 143 of 656 rej09b0071-0500 table 9.1 h8s/2264 group port functions (2) port description port and other functions name input/output and output type port 1 p17/tiocb2 p16/tioca2/ irq1 schmitt trigger input ( irq1 , irq0 ) p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tclkb p12/tclka p11 general i/o port also functioning as tpu i/o pins and interrupt input pins p10 port 3 p35/sck1/scl0 p34/rxd1/sda0 p33/txd1 p32/sck0/ irq4 p31/rxd0 general i/o port also functioning as sci_0 and sci_1 i/o pins, i 2 c bus interface i/o pins, and interrupt input pins p30/txd0 specifiable of open drain output schmitt trigger input ( irq4 ) nmos push-pull output (p35, p34, sck1) port 4 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 general input port also functioning as a/d converter analog input pins p40/an0 port 7 p77/txd2 p76/rxd2 p75/sck2 p74 p73/tmo1 p72/tmo0 general i/o port also functioning as sci_2 i/o pins and 8-bit timer i/o pins p71 p70/tmri01/tmci01
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 144 of 656 rej09b0071-0500 port description port and other functions name input/output and output type port 9 p97/an9 general input port also functioning as a/d converter analog inputs p96/an8 port f general i/o port also functioning as interrupt input pins and an a/d converter input pins pf3/ adtrg / irq3 schmitt trigger input ( irq3 ) port h general input port ph7 ph3/com4 ph2/com3 ph1/com2 general i/o port also functioning as lcd common output pins ph0/com1 port j pj7/ wkp7 /seg8 pj6/ wkp6 /seg7 pj5/ wkp5 /seg6 built-in input pull-up mos schmitt trigger input ( wkp7 to wkp0 ) pj4/ wkp4 /seg5 pj3/ wkp3 /seg4 pj2/ wkp2 /seg3 pj1/ wkp1 /seg2 general i/o port also functioning as wakeup input pins and lcd segment output pins pj0/ wkp0 /seg1 port k pk7/seg16 pk6/seg15 pk5/seg14 pk4/seg13 pk3/seg12 pk2/seg11 general i/o port also functioning as lcd segment output pins pk1/seg10 pk0/seg9
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 145 of 656 rej09b0071-0500 port description port and other functions name input/output and output type port l pl7/seg24 pl6/seg23 pl5/seg22 pl4/seg21 pl3/seg20 pl2/seg19 general i/o port also functioning as lcd segment output pins pl1/seg18 pl0/seg17 9.1 port 1 port 1 is an 8-bit i/o port and has the following registers. ? port 1 data direction register (p1ddr) ? port 1 data register (p1dr) ? port 1 register (port1) 9.1.1 port 1 data di rection register (p1ddr) p1ddr specifies input or output of the port 1 pins using the individual bits. p1ddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 146 of 656 rej09b0071-0500 bit bit name initial value r/w description 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 p10ddr 0 w 9.1.2 port 1 data register (p1dr) p1dr stores output data for port 1 pins. bit bit name initial value r/w description 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 p10dr 0 r/w 9.1.3 port 1 register (port1) port1 shows the pin states. this register cannot be modified.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 147 of 656 rej09b0071-0500 bit bit name initial value r/w description 7 p17 ? * r 6 p16 ? * r 5 p15 ? * r 4 p14 ? * r 3 p13 ? * r 2 p12 ? * r 1 p11 ? * r if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. 0 p10 ? * r note: * determined by the states of pins p17 to p10. 9.1.4 pin functions port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd * , tioca0 * , tiocb0 * , tiocc0 * , tiocd0 * , tioca1, tiocb1, tioca2, and tiocb2) and external interrupt input pins ( irq0 and irq1 ). port 1 pin functions are shown below. for the setting of the tpu channel, see section 10, 16-bit timer pulse unit (tpu). note: * supported only by the h8s/2268 group. ? p17/tiocb2/tclkd * 3 the pin function is switched as shown below acco rding to the combination of the tpu channel 2 setting, tpsc2 to tps0 bits in tcr0 * , and the p17ddr bit. tpu channel 2 setting output input or initial value p17ddr ? 0 1 p17 input p17 output pin function tiocb2 output tiocb2 input * 1 tclkd input * 2 * 3 notes: 1. this pin functions as tiocb2 input when tpu channel 2 timer operating mode is set to normal operation or phase counting mode * 3 and iob3 in tior_2 is set to 1. 2. in the h8s/2268 group, this pin functions as tclkd input when tpsc2 to tpsc0 in tcr0 are set to 111 or when channel 2 is set to phase counting mode * 3 . 3. supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 148 of 656 rej09b0071-0500 ? p16/tioca2/ irq1 the pin function is switched as shown below acco rding to the combination of the tpu channel 2 setting and the p16ddr bit. tpu channel 2 setting output input or initial value p16ddr ? 0 1 p16 input p16 output pin function tioca2 output tioca2 input * 1 irq1 input * 2 notes: 1. this pin functions as tioca2 input when tpu channel 2 timer operating mode is set to normal operation or phase counting mode * 3 and ioa3 in tior_2 is 1. 2. when this pin is used as an external interrupt pin, do not specify other functions. 3. supported only by the h8s/2268 group. ? p15/tiocb1/tclkc the pin function is switched as shown below acco rding to the combination of the tpu channel 1 setting, tpsc2 to tpsc0 bits in tcr0 * 3 and tcr2, and the p15ddr bit. tpu channel 1 setting output input or initial value p15ddr ? 0 1 p15 input p15 output pin function tiocb1 output tiocb1 input * 1 tclkc input * 2 notes: 1. this pin functions as tiocb1 input when tpu channel 1 timer operating mode is set to normal operation or phase counting mode * 3 and iob3 to iob0 in tior_1 are set to10xx. 2. this pin functions as tclkc inputs when tpsc2 to tpsc0 in tcr0 * 3 or tcr2 are set to 110 or tclkc input when channel 2 is set to phase counting mode * 3 . 3. supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 149 of 656 rej09b0071-0500 ? p14/tioca1/ irq0 the pin function is switched as shown below acco rding to the combination of the tpu channel 1 setting and the p14ddr bit. tpu channel 1 setting output input or initial value p14ddr ? 0 1 p14 input p14 output pin function tioca1 output tioca1 input * 1 irq0 input * 2 notes: 1. this pin functions as tioca1 input when tpu channel 1 timer operating mode is set to normal operation or phase counting mode * 3 and ioa3 to ioa0 in tior_1 are set to 10xx. 2. when this pin is used as an external interrupt pin, do not specify other functions. 3. supported only by the h8s/2268 group. ? p13/tiocd0 * 3 /tclkb the pin function is switched as shown below acco rding to the combination of the tpu channel 0 * 3 setting, tpsc2 to tpsc0 bits in tcr0 * 3 , tcr1 and tcr2, and the p13ddr bit. tpu channel 0 setting * 3 output input or initial value p13ddr ? 0 1 p13 input p13 output pin function tiocd0 output * 3 tiocd0 input * 1 * 3 tclkb input * 2 notes: 1. in the h8s/2268 group, this pin functions as tiocd0 input when tpu channel 0 timer operating mode is set to normal operation and iod3 to iod0 in tiorl_0 are set to 10xx. 2. this pin functions as tclkb input when tpsc2 to tpsc0 are set to 101 in any of tcr0 * 3 , tcr1 and tcr2. tclkb input, or when channel 1 is set to phase counting mode * 3 . 3. supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 150 of 656 rej09b0071-0500 ? p12/tiocc0 * 3 /tclka the pin function is switched as shown below acco rding to the combination of the tpu channel 0 * 3 setting, tpsc2 to tpsc0 bits in tcr2, tcr1 and tcr0 * 3 , and the p12ddr bit. tpu channel 0 setting * 3 output input or initial value p12ddr ? 0 1 p12 input p12 output pin function tiocc0 output * 3 tiocc0 input * 1 * 3 tclka input * 2 notes: 1. in the h8s/2268 group, tiocc0 input when tpu channel 0 timer operating mode is set to normal operation and ioc3 to ioc0 in tiorl_0 are set to 10xx. 2. this functions as tclka input when tpsc2 to tpsc0 are set to 100 in any of tcr2, tcr1 and tcr0 * 3 or when channel 1 is set to phase counting mode * 3 . 3. supported only by the h8s/2268 group. ? p11/tiocb0 * 2 the pin function is switched as shown below acco rding to the combination of the tpu channel 0 * 2 setting and the p11ddr bit. tpu channel 0 setting * 2 output input or initial value p11ddr ? 0 1 pin function tiocb0 output * 2 p11 input p11 output tiocb0 input * 1 * 2 notes: 1. in the h8s/2268 group, this pin functions as tiocb0 input when tpu channel 0 timer operating mode is set to normal operation and iob3 to iob0 in tiorh_0 are set to 10xx. 2. supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 151 of 656 rej09b0071-0500 ? p10/tioca0 * 2 the pin function is switched as shown below acco rding to the combination of the tpu channel 0 * 2 setting and the p10ddr bit. tpu channel 0 setting * 2 output input or initial value p10ddr ? 0 1 pin function tioca0 output * 2 p10 input p10 output tioca0 input * 1 * 2 notes: 1. in the h8s/2268 group, this pin functions as tioca0 input when tpu channel 0 timer operating mode is set to normal operation and ioa3 to ioa0 in tiorh_0 are set to 10xx. 2. supported only by the h8s/2268 group. 9.2 port 3 port 3 is a 6-bit i/o port. the p34, p35, and sck1 function as nmos push-pull outputs. port 3 has the following registers. ? port 3 data direction register (p3ddr) ? port 3 data register (p3dr) ? port 3 register (port3) ? port 3 open drain control register (p3odr) 9.2.1 port 3 data di rection register (p3ddr) p3ddr specifies input or output of the port 3 pins using the individual bits. p3ddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 152 of 656 rej09b0071-0500 bit bit name initial value r/w description 7, 6 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 3 pin an output port. clearing this bit to 0 makes the pin an input port. 0 p30ddr 0 w 9.2.2 port 3 data register (p3dr) p3dr stores output data for port 3 pins. bit bit name initial value r/w description 7, 6 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 p30dr 0 r/w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 153 of 656 rej09b0071-0500 9.2.3 port 3 register (port3) port3 shows the pin states. this register cannot be modified. bit bit name initial value r/w description 7, 6 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 5 p35 ? * r 4 p34 ? * r 3 p33 ? * r 2 p32 ? * r 1 p31 ? * r if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. 0 p30 ? * r note: * determined by the states of pins p35 to p30. 9.2.4 port 3 open drain control register (p3odr) p3odr controls on/off state of the pmos for port 3 pins. bit bit name initial value r/w description 7, 6 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w 0 p30odr 0 r/w when each of p33odr to p30odr bits is set to 1, the corresponding pins p33 to p30 function as nmos open drain outputs. when cleared to 0, the corresponding pins function as cmos outputs. when each of p35odr and p34odr bits is set to 1, the corresponding pins p35 and p34 function as nmos open drain outputs. when they are cleared to 0, the corresponding pins function as nmos push pull outputs.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 154 of 656 rej09b0071-0500 9.2.5 pin functions the port 3 pins also function as sci i/o input pins (txd0, rxd0, sck0, txd1, rxd1, and sck1), i 2 c bus interface i/o pins (scl0, sda0, scl1 * , and sda1 * ), and as external interrupt input pins ( irq4 and irq5 * ). as shown in figure 9.1, when the pins p34, p35, sck1, scl0, or sda0 type open drain output is used, a bus line is not affected even if the power supply for this lsi fails. use (a) type open drain output when using a bus line having a state in which the power is not supplied to this lsi. note: * supported only by the h8s/2268 group. output 0 (a) open drain output type for p34, p35, sck1, scl0, and sda0 pins note: * supported only by the h8s/2268 group. nmos off output (b) open drain output type for p33 to p30, scl1 * , and sda1 * pins pmos off input 1 input figure 9.1 types of open drain outputs the nmos push-pull outputs of the p34, p35, and sck1 pins do not reach the voltage of vcc, even when the pins are specified so that they are driven high and regardless of the load. to output the voltage of vcc, a pull-up resistor must be externally connected. notes: 1. when a pull-up resistor is externally connected, signals take longer to rise and fall. when the input signals take a long time to rise and fall, connect an input circuit that has a noise reduction function, such as a schmitt trigger circuit. 2. for high-speed operation, use an exte rnal circuit such as a level shifter. 3. for output characteristics, see the entries for high output voltage for pins p34 and p35 in table 25.15, dc characteristics (1). the value of the pull-up resistor should satisfy the specification in table 25.16, permissible output currents. the functions of port 3 pins are shown below.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 155 of 656 rej09b0071-0500 ? p35/sck1/scl0/ irq5 * 2 the pin function is switched as shown below acco rding to the combination of the ice bit in iccr_0 of iic_0, c/ a bit in smr of sci_1, cke0 and cke1 bits in scr and the p35ddr bit. ice 0 1 cke1 0 1 0 c/ a 0 1 ? 0 cke0 0 1 ? ? 0 p35ddr 0 1 ? ? ? ? pin functions p35 input pin p35 output pin sck1 output pin sck1 output pin sck1 input pin scl0 i/o pin irq5 input * 1 * 2 notes: 1. when this pin is used as an external interrupt pin, do not specify other functions. 2. supported only by the h8s/2268 group. ? p34/rxd1/sda0 the pin function is switched as shown below acco rding to the combination of the ice bit in iccr_0 of iic_0, re bit in scr of sci_1 and the p34ddr bit. ice 0 1 re 0 1 ? p34ddr 0 1 ? ? pin functions p34 input pin p34 output pin rxd1 input pin sdao i/o pin ? p33/txd1/scl1 * the pin function is switched as shown below according to the combination of the ice bit * in iccr_1 of iic_1, te bit in scr of sci_1 and the p33ddr bit. ice * 0 1 te 0 1 ? p33ddr 0 1 ? ? pin functions p33 input pin p33 output pin txd1 output pin scl1 i/o pin * note: * supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 156 of 656 rej09b0071-0500 ? p32/sck0/sda1 * 2 / irq4 the pin function is switched as shown below according to the combination of the ice bit * 2 in iccr_1 of iic_1, c/ a bit in smr of sci_0, cke0 and cke1 bits in scr and the p32ddr bit. ice * 2 0 1 cke1 0 1 0 c/ a 0 1 ? 0 cke0 0 1 ? ? 0 p32ddr 0 1 ? ? ? ? pin functions p32 input pin p32 output pin sck0 output pin sck0 output pin sck0 input pin sda1 i/o pin * 2 irq4 input * 1 notes: 1. when this pin is used as an external interrupt pin, do not specify other functions. 2. supported only by the h8s/2268 group. ? p31/rxd0 the pin function is switched as shown below acco rding to the combination of the re bit in scr of sci_0 and the p31ddr bit. re 0 1 p31ddr 0 1 ? pin functions p31 input pin p31 output pin rxd0 input pin ? p30/txd0 the pin function is switched as shown below acco rding to the combination of the te bit in scr of sci_0 and the p30ddr bit. te 0 1 p30ddr 0 1 ? pin functions p30 input pin p30 output pin txd0 output pin
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 157 of 656 rej09b0071-0500 9.3 port 4 port 4 is an 8-bit input-only port and has the following register. ? port 4 register (port4) 9.3.1 port 4 register (port4) port4 shows port 4 pin states. this register cannot be modified. bit bit name initial value r/w description 7 p47 ? * r 6 p46 ? * r 5 p45 ? * r 4 p44 ? * r 3 p43 ? * r 2 p42 ? * r 1 p41 ? * r the pin states are always read when a port 4 read is performed. 0 p40 ? * r note: * determined by the states of pins p47 to p40. 9.3.2 pin functions port 4 pins also function as a/d converter analog input pins (an0 to an7). 9.4 port 7 port 7 is an 8-bit i/o port and has the following registers. ? port 7 data direction register (p7ddr) ? port 7 data register (p7dr) ? port 7 register (port7)
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 158 of 656 rej09b0071-0500 9.4.1 port 7 data di rection register (p7ddr) p7ddr specifies input or output of the port 7 pins using the individual bits. p7ddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 p77ddr 0 w 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 7 pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 p70ddr 0 w 9.4.2 port 7 data register (p7dr) p7dr stores output data for port 7 pins. bit bit name initial value r/w description 7 p77dr 0 r/w 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 p70dr 0 r/w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 159 of 656 rej09b0071-0500 9.4.3 port 7 register (port7) port7 shows the pin states. this register cannot be modified. bit bit name initial value r/w description 7 p77 ? * r 6 p76 ? * r 5 p75 ? * r 4 p74 ? * r 3 p73 ? * r 2 p72 ? * r 1 p71 ? * r if a port 1 read is performed while p7ddr bits are set to 1, the p7dr values are read. if a port 1 read is performed while p7ddr bits are cleared to 0, the pin states are read. 0 p70 ? * r note: * determined by the states of pins p77 to p70. 9.4.4 pin functions port 7 pins also function as the 8-bit timer i/o pins (tmri01, tmci01, tmri23 * , tmci23 * , tmo0, tmo1, tmo2 * , and tmo3 * ) and sci i/o pins ( sck2, rxd2 and txd2 ). port 7 pin functions are shown below. note: * supported only by the h8s/2268 group. ? p77/txd2 the pin function is switched as shown below acco rding to the combination of the te bit in scr of sci_2 and the p77ddr bit. te 0 1 p77ddr 0 1 ? pin functions p77 input pin p77 output pin txd2 output pin
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 160 of 656 rej09b0071-0500 ? p76/rxd2 the pin function is switched as shown below acco rding to the combination of the re bit in scr of sci_2 and the p76ddr bit. re 0 1 p76ddr 0 1 ? pin functions p76 input pin p76 output pin rxd2 input pin ? p75/tmo3 * /sck2 the pin function is switched as shown below acco rding to the combination of the os3 to os0 bits in tcsr_3 * of the 8-bit timer, the c/a bit in smr of sci_2, the cke0 and cke1 bits in scr and the p75ddr bit. os3 to os0 * all bits are 0 any bit is 1 cke1 0 1 ? c/ a 0 1 ? ? cke0 0 1 ? ? ? p75ddr 0 1 ? ? ? ? pin functions p75 input pin p75 output pin sck2 output pin sck2 output pin sck2 input pin tmo3 output pin * note: * supported only by the h8s/2268 group. ? p74/tmo2 * the pin function is switched as shown below acco rding to the combination of the os3 to os0 bits in tcsr_2 * of the 8-bit timer and the p74ddr bit. os3 to os0 * all bits are 0 any bit is 1 p74ddr 0 1 ? pin functions p74 input pin p74 output pin tmo2 output pin * note: * supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 161 of 656 rej09b0071-0500 ? p73/tmo1 the pin function is switched as shown below acco rding to the combination of the os3 to os0 bits in tcsr_1 of the 8-bit timer and the p73ddr bit. os3 to os0 all bits are 0 any bit is 1 p73ddr 0 1 ? pin functions p73 input pin p73 output pin tmo1 output pin ? p72/tmo0 the pin function is switched as shown below acco rding to the combination of the os3 to os0 bits in tcsr_0 of the 8-bit timer and the p72ddr bit. os3 to os0 all bits are 0 any bit is 1 p72ddr 0 1 ? pin functions p72 input pin p72 output pin tmo0 output pin ? p71/tmri23 * /tmci23 * the pin function is switched as shown below according to the p71ddr bit. p71ddr 0 1 pin functions p71 input pin p71 output pin tmri23/tmci23 input pin * note: * supported only by the h8s/2268 group. ? p70/tmri01/tmci01 the pin function is switched as shown below according to the p70ddr bit. p70ddr 0 1 pin functions p70 input pin p70 output pin tmri01/tmci01 input pin
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 162 of 656 rej09b0071-0500 9.5 port 9 port 9 is a 2-bit input-only port and has the following register. ? port 9 register (port9) 9.5.1 port 9 register (port9) port9 shows port 9 pin states. this register cannot be modified. bit bit name initial value r/w description 7 p97 ? * r 6 p96 ? * r the pin states are always read when these bits are read. 5 to 0 ? undefined r reserved these bits are always read as undefined value and cannot be modified. note: * determined by the states of pins p97 and p96. 9.5.2 pin functions port 9 pins also function as a/d converter analog input pins (an8 and an9) and d/a converter analog output pins (da0 and da1) * . note: * supported only by the h8s/2268 group. 9.6 port f port f is a 1-bit i/o port and has the following register. ? port f data direction register (pfddr) ? port f data register (pfdr) ? port f register (portf)
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 163 of 656 rej09b0071-0500 9.6.1 port f data di rection register (pfddr) pfddr specifies input or output the port f pins using the individual bits. pfddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 3 pf3ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port f pin an output pin. clearing this bit to 0 makes the pin an input pin. 2 to 0 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 9.6.2 port f data register (pfdr) pfdr stores output data for port f pins. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 3 pf3dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 2 to 0 ? undefined ? reserved these bits are always read as undefined value and cannot be modified.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 164 of 656 rej09b0071-0500 9.6.3 port f register (portf) portf shows the pin states. this register cannot be modified. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 3 pf3 ? * r if this bit is read while pfddr is set to 1, the pfdr value is read. if this bit is read while pfddr is cleared, the pf3 pin states are read. 2 to 0 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. note: * determined by the states of pf3 pin. 9.6.4 pin functions port f pins also function as an external interrupt input pin ( irq3 ) and a/d trigger output pin ( adtrg ). port f pin functions are shown below. ? pf3/ adtrg / irq3 the pin function is switched as shown below acco rding to the combination of the trgs1 and trgs0 bits of adcr of the a/d converter and the pf3ddr bit. pf3ddr 0 1 pf3 input pin pf3 output pin pin functions adtrg input pin * 1 irq3 input pin * 2 notes: 1. when trgs0 = trgs1 = 1, port f is used as the adtrg input pin. 2. when this port is used as an external interrupt pin, do not specify other functions.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 165 of 656 rej09b0071-0500 9.7 port h port h is a 1-bit input and 4-bit i/o port. port h has the following registers. ? port h data direction register (phddr) ? port h data register (phdr) ? port h register (porth) 9.7.1 port h data direction register (phddr) phddr specifies input or output the port h pins using the i ndividual bits. phddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 3 ph3ddr 0 w 2 ph2ddr 0 w 1 ph1ddr 0 w when a pin is specified as a general purpose i/o port, setting these bits to 1 makes the corresponding port h pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 ph0ddr 0 w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 166 of 656 rej09b0071-0500 9.7.2 port h data register (phdr) phdr stores output data for port h. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 3 ph3dr 0 r/w 2 ph2dr 0 r/w 1 ph1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 ph0dr 0 r/w 9.7.3 port h register (porth) porth shows the pin states and cannot be modified. bit bit name initial value r/w description 7 ph7 ? * r when this bit is read, ph7 pin status is always read. 6 to 4 ? undefined ? reserved these bits are always read as undefined value and cannot be modified. 3 ph3 ? * r 2 ph2 ? * r 1 ph1 ? * r if these bits are read whil e the corresponding phddr bits are set to 1, the phdr value is read. if these bits are read while phddr bits are cleared to 0, the pin states are read. 0 ph0 ? * r note: * determined by the states of pins ph7 and ph3 to ph0. 9.7.4 pin functions port h pins also function as a dtmf generation circuit analog output pin (toned) * , 8-bit reload timer input pin (tmci4) * , and lcd driver common output pins (com4 to com1). port h pin functions are shown below. note: * supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 167 of 656 rej09b0071-0500 ? ph7/toned/tmci4 (h8s/2268 group) the pin function is switched as shown below acco rding to the combination of the cloe and rwoe bits in dtcr of the dtmf generation circuit. cloe, rwoe all bits are 0 any bit is 1 pin functions ph7 input pin * 1 toned output pin tmci4 input pin * 1 * 2 notes: 1. voltage applied to ph7 and tmci4 should be within the range of avss (ph7, tmci4) avcc. 2. when this port is used as tmci4 input pin, do not specify other functions. ? ph7 (h8s/2264 group) this is an input pin. voltage applied to this pin should be within the range of vss (ph7) vcc. ? ph3/com4 the pin function is switched as shown below according to the combin ation of the dts1, dts0, cmx, and sgs3 to sgs0 bits of lpcr, the sups * bit of lcr2 of the lcd controller/driver and the ph3ddr bit. sgs3 to sgs0 b'0000 h8s/2268 group: b'0001, b'001x, or b'010x h8s/2264 group: b'001x or b'010x dts1, dts0 b'xx b'0x b'10 b'11 cmx ? 0 1 0 1 ? sups * ? ? ? 0 1 ? ? ph3ddr 0 1 0 1 ? 0 1 ? ? ? pin functions ph3 input pin ph3 output pin ph3 input pin ph3 output pin com4 output pin ph3 input pin ph3 output pin setting prohibited com4 output pin com4 output pin legend: x: don?t care note: * supported only by the h8s/2268 group.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 168 of 656 rej09b0071-0500 ? ph2/com3 the pin function is switched as shown below according to the combin ation of the dts1, dts0, cmx, sgs3 to sgs0 bits of lpcr of the lcd controller/driver, and ph2ddr bit. sgs3 to sgs0 b'0000 h8s/2268 group: b'0001, b'001x or b'010x h8s/2264 group: b'001x or b'010x dts1, dts0 b'xx b'0x b'1x cmx ? 0 1 ? ph2ddr 0 1 0 1 ? pin functions ph2 input pin ph2 output pin ph2 input pin ph2 output pin com3 output pin legend: x: don?t care ? ph1/com2 the pin function is switched as shown below according to the combin ation of the dts1, dts0, cmx, sgs3 to sgs0 bits of lpcr of the lcd controller/driver, and ph2ddr bit. sgs3 to sgs0 b'0000 h8s/2268 group: b'0001, b'001x or b'010x h8s/2264 group: b'001x or b'010x dts1, dts0 b'xx b'00 other than b'00x cmx ? 0 1 ? ph1ddr 0 1 0 1 ? pin functions ph1 input pin ph1 output pin ph1 input pin ph1 output pin com2 output pin legend: x: don?t care
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 169 of 656 rej09b0071-0500 ? ph0/com1 the pin function is switched as shown below acco rding to the combina tion of the sgs3 to sgs0 bits in lpcr of the lcd controller/driver and the ph0ddr bit. sgs3 to sgs0 b'0000 h8s/2268 group: b'0001, b'001x or b'010x h8s/2264 group: b'001x or b'010x ph0ddr 0 1 ? pin functions ph0 input pin ph0 output pin com1 output pin legend: x: don?t care 9.8 port j port j is an 8-bit i/o port and has the following registers. ? port j data direction register (pjddr) ? port j data register (pjdr) ? port j register (portj) ? port j pull-up mos control register (pjpcr) ? wakeup control register (wpcr)
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 170 of 656 rej09b0071-0500 9.8.1 port j data direct ion register (pjddr) pjddr specifies input or output the port j pins using the individual bits. pjddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 pj7ddr 0 w 6 pj6ddr 0 w 5 pj5ddr 0 w 4 pj4ddr 0 w 3 pj3ddr 0 w 2 pj2ddr 0 w 1 pj1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port j pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 pj0ddr 0 w 9.8.2 port j data register (pjdr) pjdr stores output data for port j pins. bit bit name initial value r/w description 7 pj7dr 0 r/w 6 pj6dr 0 r/w 5 pj5dr 0 r/w 4 pj4dr 0 r/w 3 pj3dr 0 r/w 2 pj2dr 0 r/w 1 pj1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 pj0dr 0 r/w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 171 of 656 rej09b0071-0500 9.8.3 port j register (portj) portj shows port j pin states. this register cannot be modified. bit bit name initial value r/w description 7 pj7 ? * r 6 pj6 ? * r 5 pj5 ? * r 4 pj4 ? * r 3 pj3 ? * r 2 pj2 ? * r 1 pj1 ? * r if a port j read is performed while pjddr bits are set to 1, the pjdr values are read. if a port j read is performed while paddr bits are cleared to 0, the pin states are read. 0 pj0 ? * r note: * determined by the states of pins pj7 to pj0. 9.8.4 port j pull-up mos control register (pjpcr) pjpcr controls the input pull-up mos function for each bit. bit bit name initial value r/w description 7 pj7pcr 0 r/w 6 pj6pcr 0 r/w 5 pj5pcr 0 r/w 4 pj4pcr 0 r/w 3 pj3pcr 0 r/w 2 pj2pcr 0 r/w 1 pj1pcr 0 r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up mos for that pin. 0 pj0pcr 0 r/w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 172 of 656 rej09b0071-0500 9.8.5 wakeup control register (wpcr) wpcr controls switching of port j pin functions. for details on interrupt request flags, refer to 5.3.6, wakeup interrupt request register (iwpr). bit bit name initial value r/w description 7 wpc7 0 r/w 6 wpc6 0 r/w 5 wpc5 0 r/w 4 wpc4 0 r/w 3 wpc3 0 r/w 2 wpc2 0 r/w 1 wpc1 0 r/w when these bits are set to 1, the corresponding pjn/ wkpn pin becomes the wkpn input pin. when cleared, they become the pjn input/output pin. (n = 7 to 0) 0 wpc0 0 r/w 9.8.6 pin functions port j pins also function as wakeup input pins ( wkp7 to wkp0 ) and lcd driver segment output pins (seg8 to seg1). port j pin functions are shown below. ? pjn/ wkpn /segn + 1 the pin function is switched as shown below acco rding to the combina tion of the sgs3 to sgs0 bits in lpcr of the lcd driver/controller, wkp7 to wkp0 bits in wpcr, and pjnddr bit. sgs3 to sgs0 h8s/2268 group: b'00xx or b'0100 h8s/2264 group: b'0000, b'001x, or b'0100 b'0101 wpcn 0 1 ? pjnddr 0 1 ? ? pin functions pjn input pin pjn output pin wkpn input pin segn + 1 output pin legend: x: don?t care note: n = 7 to 0
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 173 of 656 rej09b0071-0500 9.8.7 input pull-up mos function port j has a built-in input pull-up mos function that can be controlled by software. input pull-up mos can be specified as on or off on an individual bit basis. when port j is set to port input and wakeup input, pjddr is cleared to 0, and then pjpcr is set to 1, the input pull-up mos is turned on. the input pull-up mos function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 9.2 summarizes the input pull-up mos states in port j. table 9.2 input pull-up mos states (port j) pin states reset hardware standby mode software standby mode in other operations segment output and port output off off off off port input and wakeup input on/off on/off legend: off : input pull-up mos is always off. on/off : on when pjddr = 0 and pjpcr = 1; otherwise off. 9.9 port k port k is an 8-bit i/o port and has the following registers. ? port k data direction register (pkddr) ? port k data register (pkdr) ? port k register (portk)
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 174 of 656 rej09b0071-0500 9.9.1 port k data direction register (pkddr) pkddr specifies input or output the port k pins using the i ndividual bits. pkddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 pk7ddr 0 w 6 pk6ddr 0 w 5 pk5ddr 0 w 4 pk4ddr 0 w 3 pk3ddr 0 w 2 pk2ddr 0 w 1 pk1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port k pin an output port. clearing this bit to 0 makes the pin an input port. 0 pk0ddr 0 w 9.9.2 port k data register (pkdr) pkdr stores output data for port k pins. bit bit name initial value r/w description 7 pk7dr 0 r/w 6 pk6dr 0 r/w 5 pk5dr 0 r/w 4 pk4dr 0 r/w 3 pk3dr 0 r/w 2 pk2dr 0 r/w 1 pk1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 pk0dr 0 r/w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 175 of 656 rej09b0071-0500 9.9.3 port k register (portk) portk shows port k pin states. this register cannot be modified. bit bit name initial value r/w description 7 pk7 ? * r 6 pk6 ? * r 5 pk5 ? * r 4 pk4 ? * r 3 pk3 ? * r 2 pk2 ? * r 1 pk1 ? * r if a port k read is performed while pkddr bits are set to 1, the pkdr values are read. if a port k read is performed while pkddr bits are cleared to 0, the pin states are read. 0 pk0 ? * r note: * determined by the states of pins pk7 to pk0. 9.9.4 pin functions port k pins also function as lcd driver segment output pins (seg16 to seg9). port k pin functions are shown below. ? pkn/segn + 9 the pin function is switched as shown below acco rding to the combina tion of the sgs3 to sgs0 bits in lpcr of the lcd driver/controller and pknddr bit. sgs3 to sgs0 h8s/2268 group: b'00xx h8s/2264 group: b'0000 or b'001x b'010x pknddr 0 1 ? pin functions pkn input pin pkn output pin segn + 9 output pin legend: x: don?t care note: n = 7 to 0
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 176 of 656 rej09b0071-0500 9.10 port l port l is an 8-bit i/o port and has the following registers. ? port l data direction register (plddr) ? port l data register (pldr) ? port l register (portl) 9.10.1 port l data direct ion register (plddr) plddr specifies input or output of the port l pins using the individual bits. plddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 pl7ddr 0 w 6 pl6ddr 0 w 5 pl5ddr 0 w 4 pl4ddr 0 w 3 pl3ddr 0 w 2 pl2ddr 0 w 1 pl1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port l pin an output port. clearing this bit to 0 makes the pin an input port. 0 pl0ddr 0 w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 177 of 656 rej09b0071-0500 9.10.2 port l data register (pldr) pldr stores output data for port l pins. bit bit name initial value r/w description 7 pl7dr 0 r/w 6 pl6dr 0 r/w 5 pl5dr 0 r/w 4 pl4dr 0 r/w 3 pl3dr 0 r/w 2 pl2dr 0 r/w 1 pl1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 pl0dr 0 r/w 9.10.3 port l register (portl) portl shows port l pin states. this register cannot be modified. bit bit name initial value r/w description 7 pl7 ? * r 6 pl6 ? * r 5 pl5 ? * r 4 pl4 ? * r 3 pl3 ? * r 2 pl2 ? * r 1 pl1 ? * r if a port l read is performed while plddr bits are set to 1, the pldr values are read. if a port l read is performed while plddr bits are cleared to 0, the pin states are read. 0 pl0 ? * r note: * determined by the states of pins pl7 to pl0.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 178 of 656 rej09b0071-0500 9.10.4 pin functions port l pins also function as lcd driver segment output pins (seg24 to seg17). port l pin functions are shown below. ? pln/segn + 17 the pin function is switched as shown below acco rding to the combina tion of the sgs3 to sgs0 bits in lpcr of the lcd driver/controller and plnddr bit. sgs3 to sgs0 h8s/2268 group: b'000x or b'0010 h8s/2264 group: b'00x0 b'0011 or b'010x plnddr 0 1 ? pin functions pln input pin pln output pin segn + 17 output pin legend: x: don?t care note: n = 7 to 0 9.11 port m (h8s/2268 group only) port m is an 8-bit i/o port and has the following registers. ? port m data direction register (pmddr) ? port m data register (pmdr) ? port m register (portm) 9.11.1 port m data direction register (pmddr) pmddr specifies input or output of the port m pins using the individual bits. pmddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 179 of 656 rej09b0071-0500 bit bit name initial value r/w description 7 pm7ddr 0 w 6 pm6ddr 0 w 5 pm5ddr 0 w 4 pm4ddr 0 w 3 pm3ddr 0 w 2 pm2ddr 0 w 1 pm1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port m pin an output port. clearing this bit to 0 makes the pin an input port. 0 pm0ddr 0 w 9.11.2 port m data register (pmdr) pmdr stores output data for port m pins. bit bit name initial value r/w description 7 pm7dr 0 r/w 6 pm6dr 0 r/w 5 pm5dr 0 r/w 4 pm4dr 0 r/w 3 pm3dr 0 r/w 2 pm2dr 0 r/w 1 pm1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 pm0dr 0 r/w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 180 of 656 rej09b0071-0500 9.11.3 port m register (portm) portm shows port m pin states. bit bit name initial value r/w description 7 pm7 ? * r 6 pm6 ? * r 5 pm5 ? * r 4 pm4 ? * r 3 pm3 ? * r 2 pm2 ? * r 1 pm1 ? * r if a port m read is performed while pmddr bits are set to 1, the pmdr values are read. if a port m read is performed while pmddr bits are cleared to 0, the pin states are read. 0 pm0 ? * r note: * determined by the states of pins pm7 to pm0. 9.11.4 pin functions port m pins also function as lcd driver segment output pins (seg32 to seg25). port m pin functions are shown below. ? pmn/segn + 25 the pin function is switched as shown below acco rding to the combina tion of the sgs3 to sgs0 bits in lpcr of the lcd driver/controller and pmnddr bit. sgs3 to sgs0 b'000x b'001x or b'010x pmnddr 0 1 ? pin functions pmn input pin pmn output pin segn + 25 output pin legend: x: don?t care note: n = 7 to 0
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 181 of 656 rej09b0071-0500 9.12 port n (h8s/2268 group only) port n is an 8-bit i/o port and has the following registers. ? port n data direction register (pnddr) ? port n data register (pndr) ? port n register (portn) 9.12.1 port n data di rection register (pnddr) pnddr specifies input or output of the port n pins using the individual bits. pnddr cannot be read; if it is, an undefined value will be read. the value of this register when read is undefined after a bit manipulation instruction is executed. to prevent undefined read values, do not use bit manipulation instructions to write to this register. for details, see section 2.9.4, access methods for registers with write-only bits. bit bit name initial value r/w description 7 pn7ddr 0 w 6 pn6ddr 0 w 5 pn5ddr 0 w 4 pn4ddr 0 w 3 pn3ddr 0 w 2 pn2ddr 0 w 1 pn1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port n pin an output port. clearing this bit to 0 makes the pin an input port. 0 pn0ddr 0 w
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 182 of 656 rej09b0071-0500 9.12.2 port n data register (pndr) pndr stores output data for port n pins. bit bit name initial value r/w description 7 pn7dr 0 r/w 6 pn6dr 0 r/w 5 pn5dr 0 r/w 4 pn4dr 0 r/w 3 pn3dr 0 r/w 2 pn2dr 0 r/w 1 pn1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose output port. 0 pn0dr 0 r/w 9.12.3 port n register (portn) portn shows port n pin states. bit bit name initial value r/w description 7 pn7 ? * r 6 pn6 ? * r 5 pn5 ? * r 4 pn4 ? * r 3 pn3 ? * r 2 pn2 ? * r 1 pn1 ? * r if a port n read is performed while pnddr bits are set to 1, the pndr values are read. if a port n read is performed while pnddr bits are cleared to 0, the pin states are read. 0 pn0 ? * r note: * determined by the states of pins pn7 to pn0.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 183 of 656 rej09b0071-0500 9.12.4 pin functions port n pins also function as lcd driver segment output pins (seg40 to seg33). port n pin functions are shown below. ? pnn/segn + 33 the pin function is switched as shown below acco rding to the combina tion of the sgs3 to sgs0 bits in lpcr of the lcd driver/contoller and pnnddr bit. sgs3 to sgs0 b'0000 b'0001, b'001x, or b'010x pnnddr 0 1 ? pin functions pnn input pin pnn output pin segn + 33 output pin legend: x: don?t care note: n = 7 to 0 9.13 handling of unused pins unused input pins should be fixed high or low. generally, the input pins of cmos products are high-impedance. leaving unused pins open can cause the generation of intermediate levels due to peripheral noise induction. this can result in shoot-through current inside the device and cause it to malfunction. table 9.3 lists examples of ways to handle unused pins. leave unused pins open.
section 9 i/o ports rev. 5.00 sep. 01, 2009 page 184 of 656 rej09b0071-0500 table 9.3 examples of ways to handle unused input pins port name pin handling example port 1 port 3 connect each pin to vcc (pull-up) or to vss (pull-down) via a resistor. port 4 connect each pin to avcc (pull-up) or to avss (pull-down) via a resistor. port 7 connect each pin to vcc (pull-up) or to vss (pull-down) via a resistor. port 9 connect each pin to avcc (pull-up) or to avss (pull-down) via a resistor. port f port h port j port k port l port m * connect each pin to vcc (pull-up) or to vss (pull-down) via a resistor. * ports m and n apply to the h8s/2268 group only. port n * for pins set as lcd seg pins (see 17.3.1, led port control register (lpcr)), add extra capacitance as appropriate to accommodate the lcd drive power supply capacity and the lcd used.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 185 of 656 rej09b0071-0500 section 10 16-bit timer pulse unit (tpu) the h8s/2268 group has an on-chip 16-bit timer pulse unit (tpu) comprised of three 16-bit timer channels, and the h8s/2264 group has the tpu comprised of two 16-bit timer channels. the function list of the tpu is shown in table 10.1. a block diagram of the tpu for the h8s/2268 group and that for the h8s/2264 group are shown figures 10.1 and 10.2, respectively. 10.1 features ? maximum 8-pulse input/output (h8s/2268 group) ? maximum 4-pulse input/output (h8s/2264 group) ? selection of 7 or 8 counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match ? input capture function ? counter clear operation ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture is possible register simultaneous input/output is possible by synchronous counter operation ? pwm output with any duty level is possible ? a maximum 7-phase (h8s/2268 group)/3-phase (h8s/2264 group) pwm output is possible in combination with synchronous operation ? buffer operation settable for channel 0 (h8s/2268 group only) ? phase counting mode settable independently fo r each of channels 1 and 2 (h8s/2268 group only) ? fast access via internal 16-bit bus ? 13-type interrupt sources (h8s/2268 group) ? 6-type interrupt sources (h8s/2264 group) ? register data can be transmitted automatically ? a/d converter conversion start trigger can be generated ? module stop mode can be set timtpu3b_000020030700
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 186 of 656 rej09b0071-0500 table 10.1 tpu functions item channel 0 * 1 channel 1 channel 2 count clock /1 /4 /16 /64 tclka tclkb tclkc tclkd /1 /4 /16 /64 /256 tclka tclkb /1 /4 /16 /64 /1024 tclka tclkb tclkc general registers (tgr) tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 general registers/ buffer registers * 1 tgrc_0 tgrd_0 ? ? i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output 1 output compare match output toggle output input capture function synchronous operation pwm mode phase counting mode * 1 ? buffer operation * 1 ? ? dtc activation * 1 tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture a/d converter trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 187 of 656 rej09b0071-0500 item channel 0 * 1 channel 1 channel 2 interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources * 1 3 sources * 2 ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow * 1 4 sources * 1 3 sources * 2 ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow * 1 legend: : possible ? : not possible notes: 1. supported only by the h8s/2268 group. 2. supported only by the h8s/2264 group.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 188 of 656 rej09b0071-0500 channel 2 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 control logic for channel 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control logic tstr /1 /4 /16 /64 /256 /1024 tclka tclkb tclkc tclkd legend: tstr: tsyr: tcr: tmdr: timer start register timer synchro register timer control register timer mode register timer i/o control registers (h, l) timer interrupt enable register timer status register timer general registers (a, b, c, d) tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d convertion start request signal module data bus tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u tmdr tsr tcr tiorh tier tiorl input/output pins channel 0: channel 1: channel 2: clock input internal clock: external clock: tior(h, l): tier: tsr: tgr(a, b, c, d): figure 10.1 block diagram of tpu for h8s/2268 group
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 189 of 656 rej09b0071-0500 channel 2 tmdr tsr tcr tior tier channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channel 1 to 2 tgra tcnt tgrb bus interface common tsyr control logic tstr /1 /4 /16 /64 /256 /1024 tclka tclkb tclkc legend: tstr: tsyr: tcr: tmdr: timer start register timer synchro register timer control register timer mode register timer i/o control registers timer interrupt enable register timer status register timer general registers (a, b) tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 1: channel 2: internal data bus a/d convertion start request signal module data bus tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u input/output pins channel 1: channel 2: clock input internal clock: external clock: tior: tier: tsr: tgr(a, b): figure 10.2 block diagram of tpu for h8s/2264 group
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 190 of 656 rej09b0071-0500 10.2 input/output pins table 10.2 tpu pins channel symbol i/o function all tclka input external clock a input pin (channel 1 phase counting mode a phase input * ) tclkb input external clock b input pin (channel 1 phase counting mode b phase input * ) tclkc input external clock c input pin (channel 2 phase counting mode a phase input * ) tclkd * input external clock d input pin (channel 2 phase counting mode b phase input * ) 0 * tioca0 i/o tgra_0 input capture input/output compare output/pwm output pin tiocb0 i/o tgrb_0 input capture input/output compare output/pwm output pin tiocc0 i/o tgrc_0 input capture input/output compare output/pwm output pin tiocd0 i/o tgrd_0 input capture input/output compare output/pwm output pin 1 tioca1 i/o tgra_1 input capture input/output compare output/pwm output pin tiocb1 i/o tgrb_1 input capture input/output compare output/pwm output pin 2 tioca2 i/o tgra_2 input capture input/output compare output/pwm output pin tiocb2 i/o tgrb_2 input capture input/output compare output/pwm output pin note: * supported only by the h8s/2268 group.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 191 of 656 rej09b0071-0500 10.3 register descriptions the tpu has the following registers. to distingui sh registers in each channel, an underscore and the channel number are added as a suffix to the register name; tcr for channel 0 is expressed as tcr_0. ? timer control register_0 (tcr_0) * ? timer mode register_0 (tmdr_0) * ? timer i/o control register h_0 (tiorh_0) * ? timer i/o control register l_0 (tiorl_0) * ? timer interrupt enable register_0 (tier_0) * ? timer status register_0 (tsr_0) * ? timer counter_0 (tcnt_0) * ? timer general register a_0 (tgra_0) * ? timer general register b_0 (tgrb_0) * ? timer general register c_0 (tgrc_0) * ? timer general register d_0 (tgrd_0) * ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2)
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 192 of 656 rej09b0071-0500 common registers ? timer start register (tstr) ? timer synchro register (tsyr) note: * supported only by the h8s/2268 group. 10.3.1 timer control register (tcr) the tcr registers control the tcnt operation for each channel. the h8s/2268 group tpu has a total of three tcr registers and the h8s/2264 group tpu has a total of two tcr registers, one for each channel (channels 0 to 2, or 1 and 2) . tcr register settings should be conducted only when tcnt operation is stopped. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 0 to 2 these bits select the tcnt counter clearing source. see tables 10.3 and 10.4 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 0 and 1 these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). internal clock edge selection is valid when the input clock is /4 or slower. if the input clock is / 1, this setting is ignored and count at falling edge of is selected. in the h8s/2268 group, if phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. 00: count at rising edge 01: count at falling edge 1x: count at both edges legend: x: don?t care 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 0 to 2 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables10.5 to10.7 for details.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 193 of 656 rej09b0071-0500 table 10.3 cclr0 to cclr2 (channel 0) (h8s/2268 group only) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is set by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. table 10.4 cclr0 to cclr2 (channels 1 and 2) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 1, 2 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is selected by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1 and 2. it is always read as 0 and cannot be modified.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 194 of 656 rej09b0071-0500 table 10.5 tpsc0 to tpsc2 (channel 0) (h8s/2268 group only) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input table 10.6 tpsc0 to tpsc2 (channel 1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on /256 1 setting prohibited note: * this setting is ignored when channel 1 is in phase counting mode (h8s/2268 group only).
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 195 of 656 rej09b0071-0500 table 10.7 tpsc0 to tpsc2 (channel 2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on /1024 note: * this setting is ignored when channel 2 is in phase counting mode (h8s/2268 group only). 10.3.2 timer mode register (tmdr) the tmdr registers are used to set the operating mode of each channel. the h8s/2268 group tpu has three tmdr registers and the h8s/2264 group tpu has two tmdr registers, one for each channel (channels 0 to 2, or 1 and 2). tmdr register settings shoul d be changed only when tcnt operation is stopped.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 196 of 656 rej09b0071-0500 bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 bfb 0 r/w h8s/2268 group: buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1 and 2, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation h8s/2264 group: reserved these bits are always read as 0 and cannot be modified. 4 bfa 0 r/w h8s/2268 group: buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1 and 2, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. 0: tgra operates normally 1:tgra and tgrc used together for buffer operation h8s/2264 group: reserved these bits are always read as 0 and cannot be modified. 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 0 to 3 these bits are used to set the timer operating mode. md3 is a reserved bit. in a write, it should always be written with 0. see table 10.8 for details.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 197 of 656 rej09b0071-0500 table 10.8 md0 to md3 bit 3 md3 * 1 bit 2 md2 * 2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 x x x ? legend: x: don?t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set in the h8s/2264 group or for channels 0 in the h8s/2268 group. in this case, 0 should always be written to md2. 10.3.3 timer i/o control register (tior) the tior registers control the tgr registers. the h8s/2268 group tpu has four tior registers and the h8s/2264 group tpu has two tior regi sters, two for channel 0, and one each for channels 1 and 2. care is required as tior is af fected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. in the h8s/2268 group, when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 198 of 656 rej09b0071-0500 ? tiorh_0 (h8s/2268 group only), tior_1, tior_2 bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 all 0 r/w i/o control b0 to b3 specify the function of tgrb. for details, refer to table 10.9, 10.11, and 10.12. 3 2 1 0 ioa3 ioa2 ioa1 ioa0 all 0 r/w i/o control a0 to a3 specify the function of tgra. for details, refer to table 10.13, 10.15, and 10.16. ? tiorl_0 (h8s/2268 group only) bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 all 0 r/w i/o control d0 to d3 specify the function of tgrd. for details, refer to table 10.10. 3 2 1 0 ioc3 ioc2 ioc1 ioc0 all 0 r/w i/o control c0 to c3 specify the function of tgrc. for details, refer to table 10.14.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 199 of 656 rej09b0071-0500 table 10.9 tiorh_0 (channel 0) (h8s/2268 group only) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tiocb0 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocb0 pin input capture at rising edge 1 capture input source is tiocb0 pin input capture at falling edge 1 x input capture register capture input source is tiocb0 pin input capture at both edges 1 x x setting disabled legend: x: don?t care
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 200 of 656 rej09b0071-0500 table 10.10 tiorl_0 (channel 0) (h8s/2268 group only) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tiocd0 pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocd0 pin input capture at rising edge 1 capture input source is tiocd0 pin input capture at falling edge 1 x input capture register * capture input source is tiocd0 pin input capture at both edges 1 x x setting disabled legend: x: don?t care note: * when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 201 of 656 rej09b0071-0500 table 10.11 tior_1 (channel 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tiocb1 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocb1 pin input capture at rising edge 1 capture input source is tiocb1 pin input capture at falling edge 1 x input capture register capture input source is tiocb1 pin input capture at both edges 1 x x setting disabled legend: x: don?t care
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 202 of 656 rej09b0071-0500 table 10.12 tior_2 (channel 2) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tiocb2 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 capture input source is tiocb2 pin input capture at rising edge 1 input capture register capture input source is tiocb2 pin input capture at falling edge 1 x capture input source is tiocb2 pin input capture at both edges legend: x: don?t care
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 203 of 656 rej09b0071-0500 table 10.13 tiorh_0 (channel 0) (h8s/2268 group only) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioca0 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca0 pin input capture at rising edge 1 capture input source is tioca0 pin input capture at falling edge 1 x input capture register capture input source is tioca0 pin input capture at both edges 1 x x setting disabled legend: x: don?t care
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 204 of 656 rej09b0071-0500 table 10.14 tiorl_0 (channel 0) (h8s/2268 group only) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tiocc0 pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocc0 pin input capture at rising edge 1 capture input source is tiocc0 pin input capture at falling edge 1 x input capture register * capture input source is tiocc0 pin input capture at both edges 1 x x setting disabled legend: x: don?t care note: * when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 205 of 656 rej09b0071-0500 table 10.15 tior_1 (channel 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioca1 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca1 pin input capture at rising edge 1 capture input source is tioca1 pin input capture at falling edge 1 x input capture register capture input source is tioca1 pin input capture at both edges 1 x x setting disabled legend: x don?t care
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 206 of 656 rej09b0071-0500 table 10.16 tior_2 (channel 2) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioca2 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 capture input source is tioca2 pin input capture at rising edge 1 input capture register capture input source is tioca2 pin input capture at falling edge 1 x capture input source is tioca2 pin input capture at both edges legend: x: don?t care
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 207 of 656 rej09b0071-0500 10.3.4 timer interrupt enable register (tier) the tier registers control enabling or disabling of interrupt requests for each channel. the h8s/2268 group tpu has three tier registers and the h8s/2264 group tpu has two tier registers, one for each channel (channels 0 to 2, or 1 and 2). bit bit name initial value r/w description 7 ttge 0 r/w a/d conversion start request enable enables or disables generation of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcieu 0 r/w h8s/2268 group: underflow interrupt enable enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1 and 2. in channel 0, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled h8s/2264 group: the write value should always be 0. 4 tciev 0 r/w overflow interrupt enable enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 208 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 tgied 0 r/w tgr interrupt enable d enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channel 0. in channels 1 and 2, bit 3 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgid) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled 2 tgiec 0 r/w tgr interrupt enable c enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channel 0. in channels 1 and 2, bit 2 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgic) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 209 of 656 rej09b0071-0500 10.3.5 timer status register (tsr) the tsr registers indicate the status of each channel. the h8s/2268 group tpu has three tsr registers and the h8s/2264 group tpu has two tsr re gisters, one for each channel (channels 0 to 2, or 1 and 2). bit bit name initial value r/w description 7 tcfd 1 r h8s/2268 group: count direction flag status flag that shows the direction in which tcnt counts in channels 1 and 2. in channel 0, bit 7 is reserved. it is always read as 1 and cannot be modified. 0: tcnt counts down 1: tcnt counts up h8s/2264 group: reserved this bit is always read as 1 and cannot be modified. 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcfu 0 r/(w) * 1 h8s/2268 group: underflow flag status flag that indicates that tcnt underflow has occurred when channels 1 and 2 are set to phase counting mode. only 0 can be written, for flag clearing. in channel 0, bit 5 is reserved. it is always read as 0 and cannot be modified. [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 h8s/2264 group: reserved this bit is always read as 0 and cannot be modified.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 210 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 tcfv 0 r/(w) * 1 overflow flag status flag that indicates that tcnt overflow has occurred. only 0 can be written, for flag clearing. [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfv after reading tcfv = 1 3 tgfd 0 r/(w) * 1 h8s/2268 group: input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channel 0. only 0 can be written, for flag clearing. in channels 1 and 2, bit 3 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrd and tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal and tgrd is functioning as input capture register [clearing conditions] ? when dtc is activated by tgid interrupt and the disel bit of mrb in dtc is 0 with the transfer counter other than 0 ? when 0 is written to tgfd after reading tgfd = 1 h8s/2264 group: reserved this bit is always read as 0 and cannot be modified.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 211 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 tgfc 0 r/(w) * 1 h8s/2268 group: input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channel 0. only 0 can be written, for flag clearing. in channels 1 and 2, bit 2 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrc and tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal and tgrc is functioning as input capture register [clearing conditions] ? when dtc is activated by tgic interrupt and the disel bit of mrb in dtc is 0 with the transfer counter other than 0 ? when 0 is written to tgfc after reading tgfc = 1 h8s/2264 group: reserved this bit is always read as 0 and cannot be modified.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 212 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 tgfb 0 r/(w) * 1 input capture/output compare flag b status flag that indicates the occurrence of tgrb input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgrb and tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal and tgrb is functioning as input capture register [clearing conditions] ? when dtc * 2 is activated by tgib interrupt and the disel bit of mrb in dtc * 2 is 0 with the transfer counter other than 0 ? when 0 is written to tgfb after reading tgfb = 1 0 tgfa 0 r/(w) * 1 input capture/output compare flag a status flag that indicates the occurrence of tgra input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgra and tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal and tgra is functioning as input capture register [clearing conditions] ? when dtc * 2 is activated by tgia interrupt and the disel bit of mrb in dtc * 2 is 0 with the transfer counter other than 0 ? when 0 is written to tgfa after reading tgfa = 1 notes: 1. only 0 can be written to this bit to clear the flag. 2. supported only by the h8s/2268 group.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 213 of 656 rej09b0071-0500 10.3.6 timer counter (tcnt) the tcnt registers are 16-bit readable/writable counters. the h8s/2268 group tpu has three tcnt counters and the h8s/2264 group tpu has two tcnt counters, one for each channel (h8s/2268 group: channels 0 to 2, h8s/2264 group: channels 1and 2). the tcnt counters are initialized to h'0000 by a reset, or in hardware standby mode. the tcnt counters cannot be accessed in 8-bit un its; they must always be accessed as a 16-bit unit. 10.3.7 timer general register (tgr) the tgr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture regist ers. the h8s/2268 group tpu has eight tgr registers and the h8s/2264 group tpu has four tgr registers, four for channel 0 and two each for channels 1 and 2. tgr is initialized to h'ffff at reset or in hardware stand by mode. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. in the h8s/2268 group, tgrc and tgrd for channel 0 can also be designated for operation as buffer registers. tgr buffer register combinations are tgra ? tgrc and tgrb ? tgrd.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 214 of 656 rej09b0071-0500 10.3.8 timer start register (tstr) tstr selects operation/stoppage for channels 0 to 2 in the h8s/2268 group and for channels 1 and 2 in the h8s/2264 group. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bit bit name initial value r/w description 7 to 3 ? all 0 ? reserved the write value should always be 0. 2 1 0 cst2 cst1 cst0 * 0 0 0 r/w r/w r/w counter start 0 to 2 (cst0 to cst2) these bits select operation or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_n count operation is stopped 1: tcnt_n performs count operation (n = 0 to 2) note: * in the h8s/2264 group, this bit is reserved. the write value should always be 0.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 215 of 656 rej09b0071-0500 10.3.9 timer synchro register (tsyr) tsyr selects independent operation or synchronous operation of the tcnt counters for channels 0 to 2 in the h8s/2268 group and for channels 1 and 2 in the h8s/2264 group. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. bit bit name initial value r/w description 7 to 3 ? 0 ? reserved the write value should always be 0. 2 1 0 sync2 sync1 sync0 * 0 0 0 r/w r/w r/w timer synchro 0 to 2 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_n operates independently (tcnt presetting/ clearing is unrelated to other channels) 1: tcnt_n performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible (n = 0 to 2) note: * in the h8s/2264 group, this bit is reserved. the write value should always be 0.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 216 of 656 rej09b0071-0500 10.4 interface to bus master 10.4.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the master is 16 bits wide, these registers can be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 10.3. h l bus master tcnth tcntl module data bus bus interface internal data bus figure 10.3 16-bit register access operation [bus master ? tcnt (16 bits) ] 10.4.2 8-bit registers registers other than tcnt and tgr are 8-bit. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be read and written to in 8-bit units. examples of 8-bit register access operation ar e shown in figure 10.4, 10.5, and 10.6. bus interface h internal data bus l bus master module data bus tcr figure 10.4 8-bit register access operation [bus master ? tcr (upper 8 bits) ]
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 217 of 656 rej09b0071-0500 bus interface h internal data bus l bus master module data bus tmdr figure 10.5 8-bit register access operation [bus master ? tmdr (lower 8 bits) ] bus interface h internal data bus l bus master module data bus tcr tmdr figure 10.6 8-bit register access operation [bus master ? tcr and tmdr (16 bits) ]
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 218 of 656 rej09b0071-0500 10.5 operation 10.5.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. counter operation: when one of bits cst0 to cst2 in the h8s/2268 group or one of bits cst1 and cst2 in the h8s/2264 group is set to 1 in tstr, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. 1. example of count operation setting procedure figure 10.7 shows an example of th e count operation setting procedure. operation selection select counter clock periodic counter select counter clearing source select output compare register set period free-running counter start count operation note: * in the h8s/2264 group, bits cclr1 and cclr0 in tcr. start count operation select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. for periodic counter operation, select the tgr to be used as the tcnt clearing source with bits cclr2 to cclr0 * in tcr. designate the tgr selected in [2] as an output compare register by means of tior. set the periodic counter cycle in the tgr selected in [2]. set the cst bit in tstr to 1 to start the counter operation. [1] [1] [2] [2] [3] [3] [4] [4] [5] [5] figure 10.7 example of counter operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 219 of 656 rej09b0071-0500 2. free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 10.8 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 10.8 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, a nd counter clearing by compare match is selected by means of bits cclr0 to cclr2 in the h8s/2268 group tcr or bits cclr0 and cclr1 in the h8s/2264 group tcr. after the settings have been made, tc nt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. figure 10.9 illustrates peri odic counter operation.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 220 of 656 rej09b0071-0500 tcnt value tgr h'0000 cst bit tgf note: * supported only by the h8s/2268 group. time counter cleared by tgr compare match flag cleared by software or dtc * activation figure 10.9 period ic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. example of setting procedure for waveform output by compare match figure 10.10 shows an example of the setting procedure for waveform output by compare match. input selection select waveform output mode start count operation < waveform output > select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of tior. the set initial value is output at the tioc pin unit the first compare match occurs. set the timing for compare match generation in tgr. set the cst bit in tstr to 1 to start the count operation. [1] [2] [1] [2] set output timing [3] [3] figure 10.10 example of setting procedure for waveform output by compare match 2. examples of waveform output operation figure 10.11 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, a nd settings have been made such that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 221 of 656 rej09b0071-0500 tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 10.11 example of 0 output/1 output operation figure 10.12 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 10.12 example of toggle output operation input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. 1. example of input captur e operation setting procedure figure 10.13 shows an example of the input capture operation setting procedure.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 222 of 656 rej09b0071-0500 input selection select input capture input start count designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. set the cst bit in tstr to 1 to start the count operation. [1] [2] [1] [2] figure 10.13 example of input capture operation setting procedure 2. example of input capture operation figure 10.14 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, the falling edge has been se lected as the tiocb pi n input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb time figure 10.14 example of input capture operation
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 223 of 656 rej09b0071-0500 10.5.2 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 2 in the h8s/2268 group or channels 1 and 2 in the h8s/2264 group can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 10.15 shows an example of the synchronous operation setting procedure. no yes synchronous operation selection set synchronous operation synchronous presetting set tcnt synchronous clearing clearing source generation channel? select counter clearing source start count set synchronous counter clearing start count set to 1 the sync bits in tsyr corresponding to the channels to be designated for synchronous operation. when the tcnt counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other tcnt counters. use bits cclr2 to cclr0 * in tcr to specify tcnt clearing by input capture/output compare, etc. use bits cclr2 to cclr0 * in tcr to designate synchronous clearing for the counter clearing source. set to 1 the cst bits in tstr for the relevant channels, to start the count operation. [1] [2] [3] [4] [5] note: * in the h8s/2264 group, bits ccrl1 and cclr0 in tcr. [1] [3] [5] [4] [5] [2] figure 10.15 example of synchronous operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 224 of 656 rej09b0071-0500 example of synchronous operation: figure 10.16 shows an example of synchronous operation. in this example, synchronous operation and pwm m ode 1 have been designated for channels 0 to 2 in the h8s/2268 group, tgrb_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchron ous clearing by tgrb_0 compare match, are performed for channel 0 to 2 tcnt counters, and the data set in tgrb_0 is used as the pwm cycle. for details on pwm modes, see section 10.5.4, pwm modes. tcnt0 to tcnt2 values h'0000 tioca0 tioca1 tgrb_0 synchronous clearing by tgrb_0 compare match tgra_2 tgra_1 tgrb_2 tgra_0 tgrb_1 tioca2 time figure 10.16 example of synchronous operation
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 225 of 656 rej09b0071-0500 10.5.3 buffer operation (h8s/2268 group only) buffer operation, provided for channel 0, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 10.17 shows the register combinations used in buffer operation. table 10.17 register combinat ions in buffer operation channel timer general re gister buffer register 0 tgra_0 tgrc_0 tgrb_0 tgrd_0 ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 10.17. buffer register timer general register tcnt comparator compare match signal figure 10.17 compare match buffer operation ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 10.18. buffer register timer general register tcnt input capture signal figure 10.18 input capture buffer operation
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 226 of 656 rej09b0071-0500 example of buffer operati on setting procedure: figure 10.19 shows an example of the buffer operation setting procedure. buffer operation select tgr function set buffer operation start count [1] [2] [3] [1] [2] [3] designate tgr as an input capture register or output compare register by means of tior. designate tgr for buffer operation with bits bfa and bfb in tmdr. set the cst bit in tstr to 1 start the count operation. figure 10.19 example of buff er operation setting procedure examples of bu ffer operation: 1. when tgr is an output compare register figure 10.20 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been desi gnated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been se t, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each tim e that compare match a occurs. for details on pwm modes, see section 10.5.4, pwm modes.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 227 of 656 rej09b0071-0500 tcnt value tgrb_0 h'0000 tgrc_0 tgra_0 h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgra_0 h'0450 h'0200 transfer time figure 10.20 example of buffer operation (1) 2. when tgr is an input capture register figure 10.21 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon the occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 228 of 656 rej09b0071-0500 tcnt value h'0 9 fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'0 9 fb figure 10.21 example of buffer operation (2) 10.5.4 pwm modes in pwm mode, pwm waveforms are output from the output pins. the output level can be selected as 0, 1, or toggle output in response to a compare match of each tgr. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pw m mode independently. synchronous operation is also possible. there are two pwm modes, as described below. ? pwm mode 1 h8s/2268 group: pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa0 to ioa3 and ioc0 to ioc3 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob0 to iob3 and iod0 to iod3 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, pwm output is enable up to 4 phases.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 229 of 656 rej09b0071-0500 h8s/2264 group: pwm output is generated from the tioca pin by pairing tgra with tgrb. the output specified by bits ioa0 to ioa3 in tior is output from the tioca pin at compare match a, and the output specified by bits iob0 to iob3 in tior is output at compare match b. the initial output value is the value set in tgra. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, pwm output is enable up to 2 phases. ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cy cle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, pwm output is enabled up to 7 phases in the h8s/2268 group or 3 phases in the h8s/2264 group by using also synchronous operation. the correspondence between pwm output pins and registers is shown in table 10.18. table 10.18 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 * 2 0 * 1 tgra_0 tioca0 tioca0 tgrb_0 tiocb0 tgrc_0 tiocc0 tiocc0 tgrd_0 tiocd0 1 tgra_1 tioca1 tioca1 tgrb_1 tiocb1 2 tgra_2 tioca2 tioca2 tgrb_2 tiocb2 notes: 1. supported only by the h8s/2268 group. 2. in pwm mode 2, pwm output is not possible for the tgr register in which the period is set.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 230 of 656 rej09b0071-0500 example of pwm mode setting procedure: figure 10.22 shows an example of the pwm mode setting procedure. pwm mode select counter clock select counter clearing source select waveform output level set tgr set pwm mode start count select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. use bits cclr2 to cclr0 * in tcr to select the tgr to be used as the tcnt clearing source. use tior to designate the tgr as an output compare register, and select the initial value and output value. set the cycle in the tgr selected in [2], and set the duty in the other the tgr. select the pwm mode with bits md3 to md0 in tmdr. set the cst bit in tstr to 1 start the count operation. [1] [2] [3] [4] [5] [6] [1] note: * in the h8s/2264 group, bits cclr1 and cclr0 in tcr. [2] [3] [4] [5] [6] figure 10.22 example of pwm mode setting procedure examples of pwm mode operation: figure 10.23 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in the tgrb registers are used as the duty levels.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 231 of 656 rej09b0071-0500 tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 10.23 example of pwm mode operation (1) figure 10.24 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgrb_1 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_0 to tgrd_0, tgra_1), outputting a 5-phase pwm waveform, in the h8s/2268 group. in this case, the value set in tgrb_1 is used as th e cycle, and the values set in the other tgrs are used as the duty levels. tcnt value tgrb_1 h'0000 tioca0 counter cleared by tgrb_1 compare match time tgra_1 tgrd_0 tgrc_0 tgrb_0 tgra_0 tiocb0 tiocc0 tiocd0 tioca1 figure 10.24 example of pwm mode operation (2)
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 232 of 656 rej09b0071-0500 figure 10.25 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 10.25 example of pwm mode operation (3)
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 233 of 656 rej09b0071-0500 10.5.5 phase counting mode (h8s/2268 group only) in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/d ecremented accordingly. this mode can be set for channels 1 and 2. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc0 to tpsc2 and bits ckeg0 and ckeg1 in tcr. however, the functions of bits cclr0 and cclr1 in tcr, and of tior, tier, and tgr, are valid, and input capture/compare match and interrupt functions can be used. if overflow occurs when tcnt is counting up, the tcfv flag in tsr is set; if underflow occurs when tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag reveals whether tcnt is counting up or down. table 10.19 shows the correspondence between external clock pins and channels. table 10.19 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 is set to phase counting mode tclka tclkb when channel 2 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 10.26 shows an example of the phase counting mode setting procedure. phase counting mode select phase counting mode start count select phase counting mode with bits md3 to md0 in tmdr. set the cst bit in tstr to 1 to start the count operation. [1] [2] [1] [2] figure 10.26 example of phase counting mode setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 234 of 656 rej09b0071-0500 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between tw o external clocks. there are four modes, according to the count conditions. 1. phase counting mode 1 figure 10.27 shows an example of phase counting mode 1 operation, and table 10.20 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka(channel 1) tclkc(channel 2) tclkb(channel 1) tclkd(channel 2) figure 10.27 example of phase counting mode 1 operation table 10.20 up/down-count conditions in phase counting mode 1 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level high level high level down-count low level high level low level legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 235 of 656 rej09b0071-0500 2. phase counting mode 2 figure 10.28 shows an example of phase counting mode 2 operation, and table 10.21 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka(channel 1) tclkc(channel 2) tclkb(channel 1) tclkd(channel 2) figure 10.28 example of phase counting mode 2 operation table 10.21 up/down-count conditions in phase counting mode 2 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level don?t care low level don?t care low level don?t care high level up-count high level don?t care low level don?t care high level don?t care low level down-count legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 236 of 656 rej09b0071-0500 3. phase counting mode 3 figure 10.29 shows an example of phase counting mode 3 operation, and table 10.22 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka(channel 1) tclkc(channel 2) tclkb(channel 1) tclkd(channel 2) figure 10.29 example of phase counting mode 3 operation table 10.22 up/down-count conditions in phase counting mode 3 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level don?t care low level don?t care low level don?t care high level up-count high level down-count low level don?t care high level don?t care low level don?t care legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 237 of 656 rej09b0071-0500 4. phase counting mode 4 figure 10.30 shows an example of phase counting mode 4 operation, and table 10.23 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka(channels 1) tclkc(channels 2) tclkb(channels 1) tclkd(channels 2) figure 10.30 example of phase counting mode 4 operation table 10.23 up/down-count conditions in phase counting mode 4 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level don?t care high level high level down-count low level high level don?t care low level legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 238 of 656 rej09b0071-0500 10.6 interrupt sources there are three kinds of tpu interrupt source for the h8s/2268 group; tgr input capture/compare match, tcnt overflow, and tcnt underflow. there are two kinds of tpu interrupt source for the h8s/2264 group; tgr input capture/compare match and tcnt overflow. each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by cl earing the status flag to 0. in the h8s/2268 group, relative ch annel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. for details, see section 5, interrupt controller. table 10.24 lists the tpu interrupt sources. table 10.24 tpu interrupts channel name interrupt source interrupt flag dtc activation * priority level 0 * tgi0a tgra_0 input capture/compare match tgfa_0 possible high tgi0b tgrb_0 input capture/compare match tgfb_0 possible tgi0c tgrc_0 input capture/compare match tgfc_0 possible tgi0d tgrd_0 input capture/compare match tgfd_0 possible tci0v tcnt_0 overflow tcfv_0 not possible 1 tgi1a tgra_1 input capture/compare match tgfa_1 possible tgi1b tgrb_1 input capture/compare match tgfb_1 possible tci1v tcnt_1 overflow tcfv_1 not possible tci1u * tcnt_1 underflow tcfu_1 not possible 2 tgi2a tgra_2 input capture/compare match tgfa_2 possible tgi2b tgrb_2 input capture/compare match tgfb_2 possible tci2v tcnt_2 overflow tcfv_2 not possible tci2u * tcnt_2 underflow tcfu_2 not possible low note: * supported only by the h8s/2268 group.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 239 of 656 rej09b0071-0500 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt reques t is cleared by clearing the tgf flag to 0. the h8s/2268 group tpu has eight input capture/compare match interrupts and the h8s/2264 group tpu has four input capture/compare match interrupts, four for channel 0, and two each for channels 1 and 2. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the h8s/2268 group tpu has three overflow interrupts and the h8s/2264 group tpu has two overflow interrupts, one for each channel (channels 0 to 2, or 1 and 2). underflow interrupt (h8s/2268 group only): an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by cl earing the tcfu flag to 0. the tpu has two underflow interrupts, one each for channels 1 and 2. 10.7 dtc activation (h8s/2268 group only) the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 8, data transfer controller (dtc). a total of eight tpu input capture/compare match interrupts can be used as dtc activation sources, four for channel 0, and two each for channels 1 and 2. 10.8 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to begin a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is begun. in the h8s/2268 group tpu, a total of three tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel (channels 0 to 2). while in the h8s/2264 group tpu, a total of two tgra input capture/compare match interrupts can be used, one for each channel (channels 1 and 2).
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 240 of 656 rej09b0071-0500 10.9 operation timing 10.9.1 input/output timing tcnt count timing: figure 10.31 shows tcnt count timing in internal clock operation, and figure 10.32 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n - 1 n n + 1 n + 2 falling edge rising edge figure 10.31 count timing in internal clock operation tcnt tcnt input clock external clock n - 1 n n + 1 n + 2 falling edge rising edge falling edge figure 10.32 count timing in external clock operation output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin. after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 10.33 shows output compare output timing.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 241 of 656 rej09b0071-0500 tgr tcnt tcnt input clock n nn + 1 compare match signal tioc pin figure 10.33 output compare output timing input capture signal timing: figure 10.34 shows input capture signal timing. tcnt input capture input nn + 1 n + 2 n n + 2 tgr input capture signal figure 10.34 input capture input signal timing
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 242 of 656 rej09b0071-0500 timing for counter clearing by compare match/input capture: figure 10.35 shows the timing when counter clearing on compare match is specified, and figure 10.36 shows the timing when counter clearing on i nput capture is specified. tcnt counter clear signal compare match signal tgr n n h'0000 figure 10.35 counter clea r timing (compare match) tcnt counter clear signal input capture signal tgr n h'0000 n figure 10.36 counter clear timing (input capture)
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 243 of 656 rej09b0071-0500 buffer operation timing (h8s/2268 group only): figures 10.37 and 10.38 show the timing in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd nn n nn + 1 figure 10.37 buffer operati on timing (compare match) tgra, tgrb tcnt input capture signal tgrc, tgrd n n nn + 1 n n n + 1 figure 10.38 buffer operation timing (input capture)
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 244 of 656 rej09b0071-0500 10.9.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 10.39 shows the timing for setting of the tgf flag in tsr on compare match, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n nn + 1 compare match signal tgf flag tgi interrupt figure 10.39 tgi interrupt timing (compare match)
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 245 of 656 rej09b0071-0500 tgf flag setting timing in case of input capture: figure 10.40 shows the timing for setting of the tgf flag in tsr on input capture, and tgi interrupt request signal timing. tgr tcnt input capture signal n n tgf flag tgi interrupt figure 10.40 tgi interrupt timing (input capture) tcfv flag/tcfu flag setting timing: figure 10.41 shows the timing for setting of the tcfv flag in tsr on overflow, and tciv interrupt request signal timing. figure 10.42 shows the timing for setting of the tcfu flag in tsr on underflow, and tciu interrupt request signal timing in the h8s/2268 group. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt figure 10.41 tciv interrupt setting timing
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 246 of 656 rej09b0071-0500 underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt figure 10.42 tciu interrupt setting timing (h8s/2268 group only) status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc is activated in the h8s/2268 group, the flag is cleared automatically. figure 10.43 shows the timing for status flag clearing by the cpu, and figure 10.44 shows the timing for status flag clearing by the dtc. status flag write signal address tsr address interrupt request signal tsr write cycle t1 t2 figure 10.43 timing for status flag clearing by cpu
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 247 of 656 rej09b0071-0500 interrupt request signal status flag address source address dtc read cycle t1 t2 destination address t1 t2 dtc write cycle figure 10.44 timing for status flag clearing by dtc activation (h8s/2268 group only) 10.10 usage notes 10.10.1 module stop mode setting tpu operation can be disabled or enabled using the module st op control register. the initial setting is for tpu operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 22, power-down modes. 10.10.2 input clock restrictions the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detecti on. the tpu will not operate properly at narrower pulse widths. in the h8s/2268 group phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 10.45 shows the input clock conditions in phase counting mode.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 248 of 656 rej09b0071-0500 overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 10.45 phase differe nce, overlap, and pulse width in phase counting mode (h8s/2268 group only) 10.10.3 caution on period setting when counter clearing on compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = (n + 1) where f: counter frequency : operating frequency n: tgr set value 10.10.4 contention between tc nt write and clear operations if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 10.46 shows the timing in this case.
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 249 of 656 rej09b0071-0500 counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 10.46 contention between tcnt write and clear operations 10.10.5 contention between tcnt write and increment operations if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 10.47 shows the timing in this case. tcnt input clock write signal address tcnt address tcnt tcnt write cycle t1 t2 n m tcnt write data figure 10.47 contenti on between tcnt write and increment operations
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 250 of 656 rej09b0071-0500 10.10.6 contention between tgr write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the previous value is written. figure 10.48 shows the timing in this case. compare match signal write signal address tgr address tcnt tgr write cycle t1 t2 n m tgr write data tgr n n+1 inhibited figure 10.48 contention betw een tgr write and compare match
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 251 of 656 rej09b0071-0500 10.10.7 contention between buffer register write and compare match (h8s/2268 group only) if a compare match occurs in the t2 state of a tgr write cycle, the data that is transferred to tgr by the buffer operation will be that in the buffer prior to the write. figure 10.49 shows the timing in this case. compare match signal write signal address buffer register address buffer register tgr write cycle t1 t2 n tgr n m buffer register write data figure 10.49 contention between buffer register write and compare match
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 252 of 656 rej09b0071-0500 10.10.8 contention between tgr read and input capture if an input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be that in the buffer after input capture transfer. figure 10.50 shows the timing in this case. input capture signal read signal address tgr address tgr tgr read cycle t1 t2 m internal data bus x m figure 10.50 contention between tgr read and input capture
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 253 of 656 rej09b0071-0500 10.10.9 contention between tgr write and input capture if an input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 10.51 shows the timing in this case. input capture signal write signal address tcnt tgr write cycle t1 t2 m tgr m tgr address figure 10.51 contention between tgr write and input capture
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 254 of 656 rej09b0071-0500 10.10.10 contention between buffer register write and input capture (h8s/2268 group only) if an input capture signal is generated in the t2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 10.52 shows the timing in this case. input capture signal write signal address tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 10.52 contention between buffer register write and input capture
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 255 of 656 rej09b0071-0500 10.10.11 contention between overflo w/underflow and counter clearing in the h8s/2268 group, if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. in the h8s/2264 group, if overflow and counter clearing occur simultaneously, the tcfv flag in tsr is not set and tcnt clearing takes precedence. figure 10.53 shows the operation timing when a tgr compare match is specified as the clearing source, and when h'ffff is set in tgr. counter clear signal tcnt input clock tcnt tgf flag prohibited tcfv flag h'ffff h'0000 figure 10.53 contention betw een overflow and counter clearing
section 10 16-bit timer pulse unit (tpu) rev. 5.00 sep. 01, 2009 page 256 of 656 rej09b0071-0500 10.10.12 contention between tcnt write and overf low/underflow in the h8s/2268 group, if there is an up-count or down-count in the t2 state of a tcnt write cycle and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. in the h8s/2264 group, if there is an up-count in the t2 state of a tcnt write cycle and overflow occurs, the tcnt write takes precedence a nd the tcfv flag in tsr is not set. figure 10.54 shows the operation timing when there is contention between tcnt write and overflow. write signal address tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag prohibited figure 10.54 contention be tween tcnt write and overflow 10.10.13 multiplexing of i/o pins in the h8s/2268 group, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. in the h8s/2264 group, the tclkc input pin is multiplexed with the tiocb1 i/o pin. when an external clock is input , compare match output should not be performed from a multiplexed pin. 10.10.14 interrupts in module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source, or the dtc activation source (the h8s/2268 group only). interrupts should therefore be disabled before entering module stop mode.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 257 of 656 rej09b0071-0500 section 11 8-bit timers the h8s/2268 group has an on-chip 8-bit timer module with four channels (tmr_0, tmr_1, tmr_2 and tmr_3) operating on the basis of an 8-bit counter and an 8-bit reload timer with four channels (tmr_4). the h8s/2264 group has an on-chip 8-bit timer module with two channels (tmr_0 and tmr_1) operating on the basis of an 8-bit counter. 11.1 8-bit timer module (tmr_0, tmr_1, tmr_2, and tmr_3) the 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 11.1.1 features ? selection of clock sources selected from three internal clocks ( /8, /64, and /8192) and an external clock. ? selection of three ways to clear the counters the counters can be cleared on compare-match a or b, or by an external reset signal. ? timer output controlled by two compare-match signals the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or pwm output with an arbitrary duty cycle. ? cascading of the two channels the module can operate as a 16-bit timer using channel 0 (channel 2 * ) as the upper half and channel 1 (channel 3 * ) as the lower half (16-bit count mode). channel 1 (channel 3 * ) can be used to count channel 0 (channel 2 * ) compare-match occurrences (compare-match count mode). ? multiple interrupt sources for each channel two compare-match interrupts and one overflow interrupt can be requested independently. ? generation of a/d conversion start trigger channel 0 compare-match signal can be used as the a/d conversion start trigger. ? module stop mode can be set at initialization, the 8-bit timer operation is halted. register access is enabled by canceling the module stop mode. note: * supported only by the h8s/2268 group. timh220b_000020020700
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 258 of 656 rej09b0071-0500 figure 11.1 shows a block diagram of the 8-bit timer module (tmr_0 and tmr_1). external clock note: * when a sub-clock is operating, will be sub . legend: tcora_0: time constant register a_0 tcorb_0: time constant register b_0 tcnt_0: timer counter_0 tcsr_0: timer control/status register_0 tcr_0: timer control register_0 tcora_1: time constant register a_1 tcorb_1: time constant register b_1 tcnt_1: timer counter_1 tcsr_1: timer control/status register_1 tcr_1: timer control register_1 internal clock * tmr 0 /8 /64 /81 9 2 clock 1 clock 0 compare-match a1 compare-match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo tmri01 internal bus tcora_0 comparator a_0 comparator b_0 tcorb_0 tcsr_0 tcr_0 tcora_1 comparator a_1 tcnt_1 comparator b_1 tcorb_1 tcsr_1 tcr_1 tmci01 tcnt_0 overflow 1 overflow 0 compare-match b1 compare-match b0 tmo1 a/d clock select control logic clear 0 figure 11.1 block diagram of 8-bit timer module
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 259 of 656 rej09b0071-0500 11.2 input/output pins table 11.1 summarizes the input and output pins of the 8-bit timer module. table 11.1 pin configuration channel name symbol i/o function 0 timer output tmo0 output output controlled by compare-match 1 timer output tmo1 output output controlled by compare-match timer clock input tmci01 input external clock input for the counter common to 0 and 1 timer reset input tmri01 input external reset input for the counter 2 * timer output tmo2 output output controlled by compare-match 3 * timer output tmo3 output output controlled by compare-match timer clock input tmci23 input external clock input for the counter common to 2 and 3 * timer reset input tmri23 input external reset input for the counter note: * supported only by the h8s/2268 group. 11.3 register descriptions the 8-bit timer has the following registers. for details on the module stop register, refer to section 22.1.2, module stop registers a to d (mstpcra to mstpcrd). ? timer counter_0 (tcnt_0) ? time constant register a_0 (tcora_0) ? time constant register b_0 (tcorb_0) ? timer control register_0 (tcr_0) ? timer control/status register_0 (tcsr_0) ? timer counter_1 (tcnt_1) ? time constant register a_1 (tcora_1) ? time constant register b_1 (tcorb_1) ? timer control register_1 (tcr_1) ? timer control/status register_1 (tcsr_1) ? timer counter_2 (tcnt_2) * ? time constant register a_2 (tcora_2) * ? time constant register b_2 (tcorb_2) * ? timer control register_2 (tcr_2) * ? timer control/status register_2 (tcsr_2) *
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 260 of 656 rej09b0071-0500 ? timer counter_3 (tcnt_3) * ? time constant register a_3 (tcora_3) * ? time constant register b_3 (tcorb_3) * ? timer control register_3 (tcr_3) * ? timer control/status register_3 (tcsr_3) * note: * supported only by the h8s/2268 group. 11.3.1 timer counter (tcnt) each tcnt is an 8-bit up-counter. tcnt_0 and tcnt_1 (tcnt_2 and tcnt_3) comprise a single 16-bit register, so they can be accessed together by word access. tcnt increments on pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 in tcr. tcnt can be cleared by an external reset input signal or compare-match signals a and b. counter clear bits cclr1 and cclr0 in tcr select the method of clearing. when tcnt overflows from h'ff to h'00, the overflow flag (ovf) in tcsr is set to 1. 11.3.2 time constant register a (tcora) tcora is an 8-bit readable/writable register. tcora_0 and tcora_1 (tcora_2 and tcora_3) comprise a single 16-bit register, so they can be accessed together by word access. tcora is continually compared with the valu e in tcnt. when a match is detected, the corresponding compare-match flag a (cmfa) in tc sr is set. note, however, that comparison is disabled during the t2 state of a tcora write cycle. the timer output from the tmo pin can be freely controlled by the compare-match signal a and the settings of output select bits os1 and os0 in tcsr. the initial value of tcora is h'ff. 11.3.3 time constant register b (tcorb) tcorb is an 8-bit readable/writable register. tcorb_0 and tcorb_1 (tcorb_2 and tcorb_3) comprise a single 16-bit register, so they can be accessed together by word access.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 261 of 656 rej09b0071-0500 tcorb is continually compared with the valu e in tcnt. when a match is detected, the corresponding compare-match flag b (cmfb) in tc sr is set. note, however, that comparison is disabled during the t2 state of a tcorb write cycle. the timer output from the tmo pin can be freely controlled by the compare-match signal b and the settings of output select bits os1 and os0 in tcsr. the initial value of tcorb is h'ff. 11.3.4 timer control register (tcr) tcr selects the tcnt clock source and the time at which tcnt is cleared, and controls interrupt requests. bit bit name initial value r/w description 7 cmieb 0 r/w compare-match interrupt enable b selects whether the cmfb interrupt request (cmib) is enabled or disabled when the cmfb flag in tcsr is set to 1. 0: cmfb interrupt request (cmib) is disabled 1: cmfb interrupt request (cmib) is enabled 6 cmiea 0 r/w compare-match interrupt enable a selects whether the cmfa interrupt request (cmia) is enabled or disabled when the cmfa flag in tcsr is set to 1. 0: cmfa interrupt request (cmia) is disabled 1: cmfa interrupt request (cmia) is enabled 5 ovie 0 r/w timer overflow interrupt enable selects whether the ovf interrupt request (ovi) is enabled or disabled when the ovf flag in tcsr is set to 1. 0: ovf interrupt request (ovi) is disabled 1: ovf interrupt request (ovi) is enabled 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits select the method by which tcnt is cleared 00: clearing is disabled 01: cleared on compare-match a 10: cleared on compare-match b 11: cleared on rising edge of external reset input
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 262 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 to 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 the input clock can be selected from three clocks divided from the system clock ( ). when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. 000: clock input disabled 001: /8 internal clock source, counted on the falling edge 010: /64 internal clock source, counted on the falling edge 011: /8192 internal clock source, counted on the falling edge 100: for channel 0: counted on tcnt1 overflow signal * for channel 1: counted on tcnt0 compare-matcha signal * for channel 2: counted on tcnt3 overflow signal * for channel 3: counted on tcnt2 compare-matcha signal * 101: external clock source, counted at rising edge 110: external clock source, counted at falling edge 111: external clock source, counted at both rising and falling edges note: * if the count input of channel 0 (channel 2) is the tcnt1 (tcnt3) overflow signal and that of channel 1 (channel 3) is the tcnt0 (tcnt2) compare-match signal, no incrementing clock will be generated. do not use this setting.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 263 of 656 rej09b0071-0500 11.3.5 timer control/sta tus register (tcsr) tcsr indicates status flags and controls compare-match output. ? tcsr_0 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare-match flag b [setting condition] when tcnt = tcorb [clearing conditions] ? read cmfb when cmfb = 1, then write 0 in cmfb ? the dtc * 2 is activated by the cmib interrupt and the disel bit = 0 in mrb of the dtc * 2 with the transfer counter other than 0 6 cmfa 0 r/(w) * 1 compare-match flag a [setting condition] when tcnt = tcora [clearing conditions] ? read cmfa when cmfa = 1, then write 0 in cmfa ? the dtc * 2 is activated by the cmia interrupt and disel bit = 0 in mrb of the dtc * 2 with the transfer counter other than 0 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4 adte 0 r/w a/d trigger enable enables or disables a/d converter start requests by compare-match a. 0: a/d converter start requests by compare-match a are disabled 1: a/d converter start requests by compare-match a are enabled
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 264 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits specify how the timer output level is to be changed by a compare-match b of tcorb and tcnt. 00: no change when compare-match b occurs 01: 0 is output when compare-match b occurs 10: 1 is output when compare-match b occurs 11: output is inverted when compare-match b occurs (toggle output) 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits specify how the timer output level is to be changed by a compare-match a of tcora and tcnt. 00: no change when compare-match a occurs 01: 0 is output when compare-match a occurs 10: 1 is output when compare-match a occurs 11: output is inverted when compare-match a occurs (toggle output) notes: 1. only 0 can be written to this bit, to clear the flag. 2. supported only by the h8s/2268 group.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 265 of 656 rej09b0071-0500 ? tcsr_1 and tcsr_3 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare-match flag b [setting condition] when tcnt = tcorb [clearing conditions] ? read cmfb when cmfb = 1, then write 0 in cmfb ? the dtc * 2 is activated by the cmib interrupt and the disel bit = 0 in mrb of the dtc * 2 with the transfer counter other than 0 6 cmfa 0 r/(w) * 1 compare-match flag a [setting condition] when tcnt = tcora [clearing conditions] ? read cmfa when cmfa = 1, then write 0 in cmfa ? the dtc * 2 is activated by the cmia interrupt and the disel bit = 0 in mrb of the dtc * 2 with the transfer counter other than 0 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits specify how the timer output level is to be changed by a compare-match b of tcorb and tcnt. 00: no change when compare-match b occurs 01: 0 is output when compare-match b occurs 10: 1 is output when compare-match b occurs 11: output is inverted when compare-match b occurs (toggle output)
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 266 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits specify how the timer output level is to be changed by a compare-match a of tcora and tcnt. 00: no change when compare-match a occurs 01: 0 is output when compare-match a occurs 10: 1 is output when compare-match a occurs 11: output is inverted when compare-match a occurs (toggle output) notes: 1. only 0 can be written to this bit, to clear the flag. 2. supported only by the h8s/2268 group. ? tcsr_2 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare-match flag b [setting condition] when tcnt = tcorb [clearing conditions] ? read cmfb when cmfb = 1, then write 0 in cmfb ? the dtc * 2 is activated by the cmib interrupt and the disel bit = 0 in mrb of the dtc * 2 with the transfer counter other than 0 6 cmfa 0 r/(w) * 1 compare-match flag a [setting condition] when tcnt = tcora [clearing conditions] ? read cmfa when cmfa = 1, then write 0 in cmfa ? the dtc * 2 is activated by the cmia interrupt and the disel bit = 0 in mrb of the dtc * 2 with the transfer counter other than 0
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 267 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4 ? 0 r/w reserved this bit is a readable/writable bit, but the write value should always be 0. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits specify how the timer output level is to be changed by a compare-match b of tcorb and tcnt. 00: no change when compare-match b occurs 01: 0 is output when compare-match b occurs 10: 1 is output when compare-match b occurs 11: output is inverted when compare-match b occurs (toggle output) 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits specify how the timer output level is to be changed by a compare-match a of tcora and tcnt. 00: no change when compare-match a occurs 01: 0 is output when compare-match a occurs 10: 1 is output when compare-match a occurs 11: output is inverted when compare-match a occurs (toggle output) notes: 1. only 0 can be written to this bit, to clear the flag. 2. supported only by the h8s/2268 group.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 268 of 656 rej09b0071-0500 11.4 operation 11.4.1 pulse output figure 11.2 shows an example of arbitrary duty pulse output. 1. set tcr in ccr1 to 0 and cclr0 to 1 to clear tcnt by a tcora compare-match. 2. set os3 to os0 bits in tcsr to b'0110 to output 1 by a tcora compare-match and 0 by a tcorb compare-match. by the above settings, waveforms with the cycl e of tcora and the pulse width of tcorb can be output without software intervention. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 11.2 example of pulse output
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 269 of 656 rej09b0071-0500 11.5 operation timing 11.5.1 tcnt incrementation timing figure 11.3 shows the tcnt count timing with internal clock source. figure 11.4 shows the tcnt incrementation timing with external clock source. the pulse width of the external clock for incrementation at single edge must be at least 1.5 status, and at l east 2.5 states for incrementation at both edges. the counter will not increment correctly if the pulse width is less than these values. internal clock tcnt input clock tcnt n ? 1 n n + 1 figure 11.3 count timing for internal clock input external clock input pin tcnt input clock tcnt n ? 1 n n + 1 figure 11.4 count timing for external clock input
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 270 of 656 rej09b0071-0500 11.5.2 timing of cmfa and cmfb setting when a compare-match occurs the cmfa and cmfb flags in tcsr are set to 1 by a compare-match signal generated when the tcor and tcnt values match. the compare-match signal is generated at the last state in which the match is true, just before the timer counte r is updated. therefore, when tcor and tcnt match, the compare-match signal is not generated until the next incrementation clock input. figure 11.5 shows the timing of cmf flag setting. tcnt n n + 1 tcor n compare-match signal cmf figure 11.5 timing of cmf setting 11.5.3 timing of timer output when a compare-match occurs when a compare-match occurs, the timer output ch anges as specified by the output select bits (os3 to os0) in tcsr. figure 11.6 shows the timing when the output is set to toggle at compare- match a. compare-match a signal timer output pin figure 11.6 timing of timer output
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 271 of 656 rej09b0071-0500 11.5.4 timing of compare-match cl ear when a compare-match occurs tcnt is cleared when compare-match a or b o ccurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 11.7 shows the timing of this operation. n h'00 compare-match signal tcnt figure 11.7 timing of compare-match clear 11.5.5 tcnt external reset timing tcnt is cleared at the rising edge of an exte rnal reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the width of the clearing pulse must be at least 1.5 states. figure 11.8 shows the timing of this operation. clear signal external reset input pin tcnt n h'00 n ? 1 figure 11.8 timing of clearing by external reset input
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 272 of 656 rej09b0071-0500 11.5.6 timing of overflow flag (ovf) setting ovf in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 11.9 shows the timing of this operation. ovf overflow signal tcnt h'ff h'00 figure 11.9 timing of ovf setting
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 273 of 656 rej09b0071-0500 11.6 operation with ca scaded connection if bits cks2 to cks0 in one of tcr_0 and tcr_1 (tcr_2 and tcr_3) are set to b'100, the 8- bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 (channel 2) can be counted by the timer of channel 1 (channel 3) (compare-match count mode). in the case that channel 0 is connected to channel 1 in cascade, the timer operates as described below. 11.6.1 16-bit count mode when bits cks2 to cks0 in tcr_0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ? setting of compare-match flags ? the cmf flag in tcsr_0 is set to 1 when a 16-bit compare-match occurs. ? the cmf flag in tcsr_1 is set to 1 when a lower 8-bit compare-match occurs. ? counter clear specification ? if the cclr1 and cclr0 bits in tcr_0 have been set for counter clear at compare-match, the 16-bit counter (tcnt_0 and tcnt_1 together) is cleared when a 16-bit compare- match occurs. the 16-bit counter (tcnt_0 an d tcnt_1 together) is cleared even if counter clear by the tmri01 pin has also been set. ? the settings of the cclr1 and cclr0 bits in tcr_1 are ignored. the lower 8 bits cannot be cleared independently. ? pin output ? control of output from the tmo0 pin by bits os3 to os0 in tcsr_0 is in accordance with the 16-bit compare-match conditions. ? control of output from the tmo1 pin by bits os3 to os0 in tcsr_1 is in accordance with the lower 8-bit compare-match conditions. 11.6.2 compare-match count mode when bits cks2 to cks0 in tcr_1 are b'100, tcnt_1 counts compare-match a for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clearing are in accordance with the settings for each channel.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 274 of 656 rej09b0071-0500 11.7 interrupt sources 11.7.1 interrupt sources and dtc activation the 8-bit timer can generate three types of interrupt: cmia, cmib, and ovi. table 11.2 shows the interrupt sources and priority. each interrupt source can be enabled or disabled independently by interrupt enable bits in tcr. independent signa ls are sent to the interrupt controller for each interrupt. in the h8s/2268 group, it is also possible to activate the dtc by means of cmia and cmib interrupts. table 11.2 8-bit timer interrupt sources interrupt source description flag dtc activation * interrupt priority cmia0 tcora_0 compare-match cmfa possible high cmib0 tcorb_0 compare-match cmfb possible ovi0 tcnt_0 overflow ovf not possible low cmia1 tcora_1 compare-match cmfa possible high cmib1 tcorb_1 compare-match cmfb possible ovi1 tcnt_1 overflow ovf not possible low cmia2 * tcora_2 compare-match cmfa possible high cmib2 * tcorb_2 compare-match cmfb possible ovi2 * tcnt_2 overflow ovf not possible low cmia3 * tcora_3 compare-match cmfa possible high cmib3 * tcorb_3 compare-match cmfb possible ovi3 * tcnt_3 overflow ovf not possible low note: * supported only by the h8s/2268 group. 11.7.2 a/d converter activation the a/d converter can be activated only by channel 0 compare match a. if the adte bit in tcsr0 is set to 1 when the cmfa flag is set to 1 by the occurrence of channel 0 compare match a, a request to start a/d conversion is sent to the a/d converter. if the 8-bit timer conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 275 of 656 rej09b0071-0500 11.8 usage notes 11.8.1 setting module stop mode the tmr is enabled or disabled by setting the module stop control register. in the initial state, the tmr is disabled. after the module stop mode is canceled, registers can be accessed. for details, see section 22, power-down modes. 11.8.2 contention between tcnt write and clear if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the clear takes priority, so that the count er is cleared and the write is not performed. figure 11.10 shows this operation. address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 11.10 contention be tween tcnt write and clear
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 276 of 656 rej09b0071-0500 11.8.3 contention between tcnt write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 11.11 shows this operation. address tcnt address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle by cpu counter write data figure 11.11 contention betw een tcnt write and increment
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 277 of 656 rej09b0071-0500 11.8.4 contention between tc or write and compare-match during the t2 state of a tcor write cycle, the tc or write has priority even if a compare-match occurs and the compare-match signal is disabled. figure 11.12 shows this operation. address tcor address internal write signal tcnt tcor nm t 1 t 2 tcor write cycle by cpu tcor write data nn + 1 compare-match signal prohibited figure 11.12 contention between tcor write and compare-match 11.8.5 contention between compare-matches a and b if compare-matches a and b occur at the same tim e, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match a and compare-match b, as shown in table 11.3. table 11.3 timer output priorities output setting priority toggle output high 1 output 0 output no change low
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 278 of 656 rej09b0071-0500 11.8.6 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 11.4 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in no. 3 in table 11.4, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge. this increments tcnt. erroneous incrementation can also happen when switching between internal and external clocks. table 11.4 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite nn + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 279 of 656 rej09b0071-0500 no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite nn + 1 n + 2 * 4 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite nn + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented. 11.8.7 contention between interrupts and module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 280 of 656 rej09b0071-0500 11.9 8-bit reload timer (tmr _4) (h8s/2268 group only) the 8-bit reload timer comprises an 8-bit up-counter with four channels, and has two functions, the interval function and automatic reload function. 11.9.1 features ? selection of clock sources ? selected from 14 internal clocks ( /32768, /8192, /2048, /512, /128, /32, /8, /2, sub /256, sub /128, sub /64, sub /32, sub /8 and sub /2) and an external clock. ? interrupts requested by counter overflow ? operation with cascaded connection (the lower the channel number, the higher the bit in the connected timer) ? connecting two timers (channels 4 and 5, channels 5 and 6, or channels 6 and 7): the module operates as a 16-bit timer ? connecting three timers (channels 4 to 6 or channels 5 to 7): the module operates as a 24- bit timer ? connecting four timers (channels 4 to 7): the module operates as a 32-bit timer ? module stop mode can be set ? at initialization, the 8-bit reload timer is ha lted. register access is enabled by canceling the module stop mode. figure 11.13 shows a block diagram of the 8-bit reload timer.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 281 of 656 rej09b0071-0500 tcr_4 clock select tcnt_4 tlr_4 ovi4 ovi5 ovi6 ovi7 tcr_5 clock select tcnt_5 tlr_5 tcr_6 clock select tcnt_6 tlr_6 tcr_7 clock select tcnt_7 tlr_7 interrupt contorol bus interface internal clock /2 /8 /32 /128 /512 /2048 /81 9 2 /32768 sub /2 sub /8 sub /32 sub /64 sub /128 sub /256 internal bus external clock tmci4 reload tcr_4: tcnt_4: tlr_4: tcr_5: tcnt_5: tlr_5: legend: timer control register 4 timer counter 4 timer reload register 4 timer control register 5 timer counter 5 timer reload register 5 tcr_6: tcnt_6: tlr_6: tcr_7: tcnt_7: tlr_7: timer control register 6 timer counter 6 timer reload register 6 timer control register 7 timer counter 7 timer reload register 7 module bus figure 11.13 block diagram of 8-bit reload timer 11.9.2 input/output pins the following table shows the pin configuration for the 8-bit timer module. name symbol i/o function timer clock input pin tmci4 input external clock input for the counter note: voltage applied to the tmci4 input pin should be within the range, avss tmci4 avcc.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 282 of 656 rej09b0071-0500 11.10 register descriptions the 8-bit reload timer has the following registers. for details on the module stop control register, refer to section 22.1.2, module stop control registers a to d (mstpcra to mstpcrd). ? timer control register (tcr) ? timer counter (tcnt) ? timer reload register (tlr) tcnt or tlr can operate as a 16-bit timer using tcnt_4 or tlr_4 (tcnt_6 or tlr_6) as the upper half and tcnt_5 or tlr_5 (tcnt_7 or tlr_7) as the lower half. 11.10.1 timer control registers 4 to 7 (tcr_4 to tcr_7) tcr selects the automatic reload function and tcnt clock source, and controls interrupt requests. bit bit name initial value r/w description 7 arsl 0 r/w automatic reload function select selects the automatic reload function 0: the interval function is selected 1: the automatic reload function is selected 6 ovf 0 r/(w) * timer overflow flag indicates that tcnt overflows from h'ff to h'00. 0: [clearing condition] read ovf when ovf = 1, then write 0 in ovf 1: [setting condition] when tcnt overflows from h'ff to h'00 5 ovie 0 r/w timer overflow interrupt enable selects whether the ovf interrupt request (ovi) is enabled or disabled when the ovf flag in tcsr is set to 1. 0: ovf interrupt request (ovi) is disabled 1: ovf interrupt request (ovi) is enabled 4, 3 ? all 1 ? reserved these bits are always read as 1 and cannot be modified.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 283 of 656 rej09b0071-0500 bit bit name initial value r/w description clock select 2 to 0 the input clock can be selected from internal clocks and an external clock, which are divided from the system clock ( ) or subclock ( sub ). channel4 channel5 channel6 channel7 000: /32768 /8192 /32768 /8192 001: /2048 /512 /2048 /512 010: /128 /32 /128 /32 011: /8 /2 /8 /2 100: sub /256 sub /128 sub /256 sub /128 101: sub /64 sub /32 sub /64 sub /32 2 to 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w 110: sub /8 sub /2 sub /8 sub /2 111: tcnt_5 overflow tcnt_6 overflow tcnt_7 overflow count of the rising clock of the external clock. note: * only a 0 can be written to this bit, to clear the flag. 11.10.2 timer counters 4 to 7 (tcnt4 to tcnt7) each tcnt is an 8-bit readable up-counter and increments on clock pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 in tcr tcnt_4 and tcnt_5, or tcnt_6 and tcnt_7 comprise a single 16-bit register, and can be accessed simultaneously by word access. when tcnt overflows from h'ff to h'00, the overflow flag (ovf) in tcr is set to 1. tcnt is initialized to h'00 by a reset or in hardware standby mode. 11.10.3 time reload registers 4 to 7 (tlr_4 to tlr_7) each tlr is an 8-bit writable register and sets a reload value for tcnt. when a reload value is set to tlr, the value is simultaneously load to tcnt and incrementation starts from the value. when tcnt overflows during automatic reload operation, the tlr value is written to tcnt. therefore, the overflow cycle can be set within the range from 1 to 256 input clock cycles.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 284 of 656 rej09b0071-0500 tlr_4 and tlr_5, or tlr_6 and tlr_7 comprise a single 16-bit register, and can be accessed simultaneously by word access. tlr is initialized to h'00 by a reset or in hardware standby mode. 11.11 operation 11.11.1 interval timer operation when the arsl bit in tcr is set to 0, the timer operates as an interval timer. after a module stop mode is canceled, the timer continues incrementation as an interval timer without stopping because tcnt is initialized to h' 00 and tlr is cleared to 0 by a reset. the input clock source can be selected from 14 internal clocks output from the prescaler unit and an external clock from the tmci4 input pin, using the cks2 to cks0 bits in tcr. when a clock is input after the tcnt value has been h'ff, the timer overflows and ovf in tcr is set to 1. at this time, if ovie in tcr is 1, an interrupt is generated. when an overflow occurs, the tcnt count value is cleared to h'00 and tcnt restarts incrementation. if a value is set to tlr during interval timer operation, the value is also written to tcnt. this operation timing is shown in figure 11.14. h'ff h'00 time overflow overflow overflow overflow mstpd5 = 0 arsl = 0 ovf ovf ovf ovf tcnt value ovf: timer overflow interrupt request generation figure 11.14 operation in interval timer mode
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 285 of 656 rej09b0071-0500 11.11.2 automatic reload timer operation when the arsl bit in tcr is set to 1, the timer operates as an automatic reload timer. when a reload value is set to tlr, the value is also loaded to tcnt simultaneously, and tcnt starts incrementation from the value. if a clock is input after the tcnt count value r eaches h'ff, the timer overf lows, the tlr value is written to tcnt, and incrementation is continued from the value. therefore, the overflow cycle can be set within the range from 1 to 256, using a tlr value. clock sources and interrupts in automatic reload operation are the same as those in interval operation. if tlr is re-set during automatic reload operation, the value is also set to tcnt. this operation timing is shown in figure 11.15. h'ff h'80 h'40 h'00 tcnt value mstpd5 = 0 arsl = 0 arsl = 1 tlr setting (h'80)) tlr setting (h'40) ovf ovf ovf ovf ovf ovf: timer overflow interrupt request generation ovf time overflow overflow overflow overflow overflow overflow figure 11.15 operation in automatic reload timer mode 11.11.3 cascaded connection ? read of tcnt the channel relationship for cascaded connection is shown in figure 11.16. when accessing beyond the word area, for exam ple, when a cascaded connection including channels 5 and 6 is created as shown in (3), and (6) to (8) in the figure, the counter value of the lower channel is read when tcnt5 is read, a nd the data is stored in the tcnt register. for case (7) where channels 5 to 7 are cascaded, the counter values of channels 6 and 7 are read when tcnt5 is read, and the data is stor ed in tcnt6/7 registers. accordingly, when reading cascaded tcnt, read from the upper channel.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 286 of 656 rej09b0071-0500 for a word connection, access in word units. cascaded connection upper lower 1 2 3 4 5 6 7 8 channel 4 channel 4 channel 4 channel 4 channel 4 channel 4 channel 4 channel 4 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 channel 5 channel 6 channel 7 figure 11.16 channel relationship of cascaded connection ? write to tlr when writing to the cascaded tlr, even if a si ngle channel of tlr is written, the system regards that the entire channels of the cascaded tlr are rewritten. at this point in time, the value in the entire cascaded tlr is loaded into the corresponding tcnt. the timer operation starts at the tlr value that is mo st-recently written in tlr access cycles. ? operation clock although each channel usually operates on an individual clock, a cascaded channel operates on the same clock. the operation clock for the lo west cascaded channel is used as a common clock of each channel. in this case, the setting for the cl ocks of the channels other than the lowest channel is disabled. ? automatic reload function select and operation timing
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 287 of 656 rej09b0071-0500 although the automatic reload function is usually set and implemented in individual channel, a cascaded channel operates according to the setting for the automatic reload function of the highest channel. in this case, the automatic reload function settings for the channels other than the highest channel are disabled. when the automatic reload function is en abled for cascaded channel, the tlr setting value of each channel is automatica lly reloaded simultane ously in the reload timing of the highest channel. ? timer overflow flag (ovf) although an ovf is usually set to an individual channel independently, an ovf is set to the highest channel of a cascaded channel. in this cas e, ovfs of the channels other than that of the highest channel is disabled. 11.12 usage notes 11.12.1 conflict between write to tlr and count up/automatic reload even if a count up occurs in the t2 state during tlr write cycles, the counter is not incremented and tlr write (load to tcnt) is carried out instead (as in figure 11.11). likewise, if an automatic reload occurs during write cycles, tlr write (l oad to tcnt) is carried out instead. 11.12.2 switchover of internal cl ock and tcnt operation depending on the timing which the internal clock is switched, tcnt may be incremented (see table 11.4). likewise, when the clock pulse is changed ( and sub ), tcnt may be incremented, and may not in some cases. therefore, when the in ternal clock is changed, resume timer operation by resetting tlr (write h'00 to tlr when the interval timer is in operation). 11.12.3 interrupt during module stop when module stop mode is entered with an interrupt being requested, the cause of an interrupt to the cpu cannot be cleared. enter module stop mode after, for example, disabling an interrupt request.
section 11 8-bit timers rev. 5.00 sep. 01, 2009 page 288 of 656 rej09b0071-0500
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 289 of 656 rej09b0071-0500 section 12 watchdog timer (wdt) the watchdog timer (wdt) is an 8-bit timer that can generate an internal reset signal for this lsi if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. the block diagram of the wdt is shown in figures 12.1 to 12.3. 12.1 features ? selectable from eight counter input clocks for wdt_0 selectable from 16 counter input clocks for wdt_1 ? switchable between watchdog timer mode and interval timer mode in watchdog timer mode ? if the counter in wdt_0 overflows, it is possible to select whether this lsi is internally reset or not. ? if the counter in wdt_1 overflows, it is possible to select whether this lsi is internally reset or the internal nmi interrupt is generated. in interval timer mode ? if the counter overflows, the wdt generates an interval timer interrupt (wovi). wdt0105b_000020030700
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 290 of 656 rej09b0071-0500 overflow interrupt control wovi0 (interrupt request signal) internal reset signal * 1 reset control rstcsr tcnt_0 tcsr_0 /2 /64 /128 /512 /2048 /81 9 2 /32768 /131072 clock clock select internal clock * 2 bus interface module bus tcsr_0: tcnt_0: rstcsr: notes: 1. the type of internal reset signal depends on a register setting. 2. when a sub-clock is operating, will be sub . timer control/status register0 timer counter0 reset control/status register wdt legend: internal bus figure 12.1 block diagram of wdt_0 overflow interrupt control wovi1 (interrupt request signal) internal nmi (interrupt request signal) internal reset signal * reset control tcnt_1 tcsr_1 /2 /64 /128 /512 /2048 /81 9 2 /32768 /131072 sub /2 sub /4 sub /8 sub /16 sub /32 sub /64 sub /128 sub /256 clock clock select internal clock bus interface module bus internal bus wdt tcsr_1: tcnt_1: note: * the type of internal reset signal depends on a register setting. timer control/status register1 timer counter1 legend: figure 12.2 block diagram of wdt_1
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 291 of 656 rej09b0071-0500 12.2 register descriptions the wdt has the following registers. to preven t accidental overwriting, tcsr and tcnt have to be written to by a different met hod to normal registers. for details, refer to section 12.5.1, notes on register access. ? timer counter (tcnt) ? timer control/status register (tcsr) ? reset control/status register (rstcsr) 12.2.1 timer counter (tcnt) tcnt is an 8-bit readable/writa ble up-counter. tcnt is initialized to h'00 when the tme bit in tcsr is cleared to 0. to initialize tcnt to h?00 while the timer is operating, write h?00 to tcnt directly. see 12.5.7, notes on initializing tcnt by using the tme bit. 12.2.2 timer control/sta tus register (tcsr) tcsr functions include selecting the clock source to be input to tcnt and the timer mode. ? tcsr_0 bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcnt has overflowed. only a 0 can be written to this bit, to clear the flag. [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing condition] cleared by reading tcsr * 2 when ovf = 1, then writing 0 to ovf
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 292 of 656 rej09b0071-0500 bit bit name initial value r/w description 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode (interval timer interrupt (wovi) is requested to cpu) 1: watchdog timer mode (internal reset selectable) 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4, 3 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 0 to 2 selects the clock source to be input to tcnt. the overflow frequency * 3 for = 20 mhz is enclosed in parentheses. 000: clock /2 (frequency: 25.6 s) 001: clock /64 (frequency: 819.2 s) 010: clock /128 (frequency: 1.6 ms) 011: clock /512 (frequency: 6.6 ms) 100: clock /2048 (frequency: 26.2 ms) 101: clock /8192 (frequency: 104.9 ms) 110: clock /32768 (frequency: 419.4 ms) 111: clock /131072 (frequency: 1.68 s) notes: 1. only 0 can be written, for flag clearing. 2. when the ovf flag is polled with the interval timer interrupt disabled, read the ovf bit while it is 1 at least twice. 3. the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs.
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 293 of 656 rej09b0071-0500 ? tcsr_1 bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcnt has overflowed. only a 0 can be written to this bit, to clear the flag. [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing conditions] cleared by reading tcsr * 2 when ovf = 1, then writing 0 to ovf 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode (interval timer interrupt (wovi) is requested to cpu) 1: watchdog timer mode (internal reset or nmi interrupt is requested to cpu) 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4 pss 0 r/w prescaler select selects the clock source input to tcnt of wdt_1 0: tcnt counts divided clock of -base prescaler (psm). 1: tcnt counts divided clock of sub -base prescaler (pss) 3 rst/ nmi 0 r/w reset or nmi selects either a power-on reset or the nmi interrupt request when tcnt overflows in watchdog timer mode. 0: nmi interrupt is requested 1: reset is requested
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 294 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 0 to 2 selects the clock source to be input to tcnt. the overflow frequency * 3 for = 20 mhz or sub = 32.768 khz is enclosed in parentheses. when pss = 0: 000: clock /2 (frequency: 25.6 s) 001: clock /64 (frequency: 819.2 s) 010: clock /128 (frequency: 1.6 ms) 011: clock /512 (frequency: 6.6 ms) 100: clock /2048 (frequency: 26.2 ms) 101: clock /8192 (frequency: 104.9 ms) 110: clock /32768 (frequency: 419.4 ms) 111: clock /131072 (frequency: 1.68 s) when pss = 1: 000: clock sub /2 (frequency: 15.6 ms) 001: clock sub /4 (frequency: 31.3 ms) 010: clock sub /8 (frequency: 62.5 ms) 011: clock sub /16 (frequency: 125 ms) 100: clock sub /32 (frequency: 250 ms) 101: clock sub /64 (frequency: 500 ms) 110: clock sub /128 (frequency: 1 s) 111: clock sub /256 (frequency: 2 s) notes: 1. only 0 can be written, for flag clearing. 2. when the ovf flag is polled with the interval timer interrupt disabled, read the ovf bit while it is 1 at least twice 3. the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs.
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 295 of 656 rej09b0071-0500 12.2.3 reset control/status register (rstcsr) (only wdt_0) rstcsr controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, and not by the wdt internal reset signal caused by overflows. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode, and only 0 can be written, to clear the flag. [setting condition] set when tcnt overflows (changed from h'ff to h'00) in watchdog timer mode [clearing condition] cleared by reading rstcsr when wovf = 1, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not a reset signal is generated in the chip if tcnt overflows during watchdog timer operation. 0: reset signal is not generated even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: reset signal is generated if tcnt overflows 5 ? 0 r/w reserved this bit can be read from and written to. however, the write value should always be 0. 4 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. note: * only 0 can be written, to clear the flag.
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 296 of 656 rej09b0071-0500 12.3 operation 12.3.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it bit in tcsr and the tme bit to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. thus, tcnt does not overflow while the system is operating normally. when the wdt is used as a watchdog timer and the rste bit in rstcsr of wdt_0 is set to 1, and if tcnt overflows without being rewritten because of a system malfunction or other error, an internal reset signal for this lsi is output for 518 system clocks. when the rst/ nmi bit in tcsr of wdt_1 is set to 1, and if tcnt overflows, the internal reset signal is output for 516 system clock periods. when the rst/ nmi bit is cleared to 0, an nmi interrupt request is generated (for 515 or 516 system clock periods when the clock source is set to sub (pss = 1)). an internal reset request from the watchdog timer and a reset input from the res pin are both treated as having the same vector. if a wdt internal reset request and the res pin reset occur at the same time, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. an nmi request from the watchdog timer and an interrupt request from the nmi pin are both treated as having the same vector. so, avoid handling an nmi request from the watchdog timer and an interrupt request from the nmi pin at the same time.
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 297 of 656 rej09b0071-0500 tcnt value h'00 time h'ff wt/ it = 1 tme = 1 write h'00' to tcnt wt/ it = 1 tme = 1 write h'00' to tcnt 518 system clock (wdt0) 515/516 system clock (wdt1) internal reset signal * wt/ it : tme: note: * in the case of wdt_0, the internal reset signal is generated only when the rste bit is set to 1. in the case of wdt_1,either the internal reset or the nmi interrupt is generated. overflow internal reset is generated wovf = 1 timer mode select bit timer enable bit legend: figure 12.3 watchdog timer mode operation 12.3.2 interval timer mode to use the wdt as an in ternal timer, set the wt/ it and tme bits in tcsr to 0. when the wdt is used as an in terval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows. (the nmi interrupt request is not generated.) therefore, an interrupt can be generated at intervals. tcnt value h'00 time h'ff wt/ it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt request generation wovi wovi wovi figure 12.4 interval timer mode operation
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 298 of 656 rej09b0071-0500 12.3.3 timing of setting overflow flag (ovf) the ovf flag is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 12.5. tcnt h'ff h'00 ovf overflow signal (internal signal) figure 12.5 timing of ovf setting 12.3.4 timing of setting watchdog timer overflow flag (wovf) with wdt_0 the wovf bit in rstcsr is set to 1 if tcnt overflows in watchdog timer mode. if tcnt overflows while the rste bit in rstcsr is set to 1, an internal is generated for the entire chip. (wovi interrupt is not generated.) this timing is illustrated in figure 12.6. tcnt h'ff h'00 overflow signal (internal signal) wovf internal reset signal 518 states (wdt_0) 515/516 states (wdt_1) figure 12.6 timing of wovf setting
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 299 of 656 rej09b0071-0500 12.4 interrupt sources during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is re quested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. if an nmi request has been chosen in the watchdog timer mode, an nmi request is generated when a tcnt overflow occurs. table 12.1 wdt interrupt source name interrupt source interrupt flag wovi tcnt overflow (interval timer mode) ovf nmi tcnt overflow (watchdog timer mode) ovf 12.5 usage notes 12.5.1 notes on register access the watchdog timer?s tcnt and tcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. (1) writing to tcnt and tcsr word transfer instructions must be used to write to tcnt and tcsr. these registers cannot be written with byte transfer instructions. this is shown in figure 12.7. for writing, tcnt and tcsr are a llocated to the same address. to write to tcnt, transfer a word in which the upper byte is h'5a and the lower byte is the write data. to write to tcsr, transfer a word in which the upper byte is h'a5 and the lower byte is the write data. when these transfer operations are performed, the lowe r byte data is written to tcnt or tcsr. tcnt write tcsr write address: address: 15 8 7 0 h'5a h'ff74 write data write data 15 8 7 0 h'a5 h'ff74 figure 12.7 writing to tcnt, tcsr (wdt_0)
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 300 of 656 rej09b0071-0500 (2) writing to rstcsr use word transfer operations to write to rstcsr. this register cannot be written using byte transfer instructions. this is shown in figure 12.8. the method used to write a 0 to the wovf bit and the method used to write the rste and rsts bits are different. to write a 0 to the wovf bit, set the upper byte to h'a5 and the lower byte to h'00 and transfer that data. this will clear the wovf bit to 0. this operation does not affect the rste and rsts bits. to write the rste and rsts bits, set the upper byte to h'5a and the lower byte to the data to be written and transfer that data. this will write the data in bits 6 and 5 of the lower byte to the rste and rsts bits. this operation does not affect the wovf bit. when writing 0 to the wovf bit when writing to the rste and rsts bits address: address: 15 8 7 0 h'a5 h'ff76 h'00 write data 15 8 7 0 h'5a h'ff76 figure 12.8 writing to rstcsr (3) reading tcnt, tcsr, and rstcsr (wdt _ 0) these registers are read in the same way as ot her registers. the read addresses are h'ff74 for tcsr and h'ff77 for rstcsr.
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 301 of 656 rej09b0071-0500 12.5.2 contention betw een timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 12.9 shows this operation. address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 12.9 contention betw een tcnt write and increment 12.5.3 changing value of cks2 to cks0 if bits cks0 to cks2 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must be used to stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks0 to cks2. 12.5.4 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer while the wdt is operating, errors could occur in the incrementation. software must be used to stop the watchdog timer (by clearing the tme bit to 0) before switching the mode.
section 12 watchdog timer (wdt) rev. 5.00 sep. 01, 2009 page 302 of 656 rej09b0071-0500 12.5.5 internal reset in watchdog timer mode this lsi is not reset internally if tcnt overf lows while the rste bit is cleared to 0 during watchdog timer operation, however tcnt_0 and tcsr_0 of the wdt_0 are reset. tcnt, tcsr, or rstcr cannot be written to for 132 states following an overflow. during this period, any attempt to read the wovf flag is not acknowledged. accordingly, wait 132 states after overflow to write 0 to the wovf flag for clearing. 12.5.6 ovf flag clearing in interval timer mode when the ovf flag setting conflicts with the ovf flag reading in interval timer mode, writing 0 to the ovf bit may not clear the flag even though the ovf bit has been read while it is 1. if there is a possibility that the ovf flag setting and readi ng will conflict, such as when the ovf flag is polled with the interval timer interrupt disabled, read the ovf bit while it is 1 at least twice before writing 0 to the ovf bit to clear the flag. 12.5.7 notes on initializing tcnt by using the tme bit when the sub (subckock) division clock is selected as the tcnt input clock (pss in tcsr set to 1) and, after tme in tcsr is cleared to 0 to initialize the counter (t cnt) while the counter (tcnt) is operating in the high-speed mode or medium-speed mode, tcnt is restarted by setting tme to 1 once again, tcnt may not be correctly initialized. in such cases, use either of the following methods to initialize tcnt: (1) write h'00 to tcnt. (2) in subactive mode, clear the tme bit to 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 303 of 656 rej09b0071-0500 section 13 serial communication interface (sci) this lsi has three independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function) . the sci also supports an ic card (smart card) interface conforming to iso/iec 7816-3 (iden tification card) as a serial communication interface extension function. 13.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually indepe ndent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the tran smitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected external clock can be selected as a transfer clock source (except for in smart card interface mode). ? choice of lsb-first or msb-first transfer (except in the case of asynchronous mode 7-bit data) ? four interrupt sources transmit-end, transmit-data-empty, r eceive-data-full, and receive error ? that can issue requests. the transmit-data-empty interrupt and receive da ta full interrupts can be used to activate the data transfer controller (dtc) (h8s/2268 group only). ? module stop mode can be set asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be de tected by reading the rxd pin le vel directly in the case of a framing error sci0025b_000020020700
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 304 of 656 rej09b0071-0500 ? average transfer rate generator (sci_0): 720 kbps, 460.784 kbps, or 115.196 kbps can be selected at 16 mhz operation. ? transfer rate clock can be input from the tpu (sci_0). ? communications between multi-processors are possible. clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected smart card interface ? automatic transmission of error signa l (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 305 of 656 rej09b0071-0500 figure 13.1 shows a block diagram of the sci_0, and figure 13.2 shows that of the sci1 and sci_2. rxd0 txd0 sck0 tei txi rxi eri scmr ssr scr smr semr brr rdr tsr rsr tdr tioca1 tclka tioca2 tpu external clock transmission/ reception control baud rate generator module data bus bus interface parity generation internal data bus clock /4 /16 /64 rsr: rdr: tsr: tdr: smr: receive shift register receive data register transmit shift register transmit data register serial mode register scr: ssr: scmr: brr: semr: serial control register serial status register smart card mode register bit rate register serial expansion mode register legend: parity check 10.667 mhz operation 115.152 kbps 460.606 kbps 16 mhz operation 115.1 9 6 kbps 460.784 kbps 720 kbps average transfer rate generator figure 13.1 block diagram of sci_0
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 306 of 656 rej09b0071-0500 rxd txd sck clock external clock /4 /16 /64 tei txi rxi eri rsr: rdr: tsr: tdr: smr: scr: ssr: scmr: brr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register smart card mode register bit rate register scmr ssr scr smr transmission/ reception control baud rate generator brr module data bus bus interface rdr tsr rsr parity generation parity check legend: tdr internal data bus figure 13.2 block diagram of sci_1 or sci_2
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 307 of 656 rej09b0071-0500 13.2 input/output pins table 13.1 shows the pin configuration for each sci channel. table 13.1 pin configuration channel pin name * i/o function sck0 i/o sci0 clock input/output rxd0 input sci0 receive data input 0 txd0 output sci0 transmit data output sck1 i/o sci1 clock input/output rxd1 input sci1 receive data input 1 txd1 output sci1 transmit data output sck2 i/o sci2 clock input/output 2 rxd2 input sci2 receive data input txd2 output sci2 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 13.3 register descriptions the sci has the following register s for each channel. for details on register addresses and register states during each process, refer to section 24, list of registers. the serial mode register (smr), serial status register (ssr), and serial control register (scr) are described separately for normal serial communication interface mode and smart ca rd interface mode because their bit functions differ in part. ? receive shift register (rsr) ? receive data register (rdr) ? transmit data register (tdr) ? transmit shift register (tsr) ? serial mode register (smr) ? serial control register (scr) ? serial status register (ssr) ? smart card mode register (scmr) ? bit rate register (brr)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 308 of 656 rej09b0071-0500 other than the above registers, sci_0 has the following register. ? serial expansion mode register (semr0) 13.3.1 receive shift register (rsr) rsr is a shift register that is used to receive se rial data input to the rxd pin and convert it into parallel data. when one byte of data has been r eceived, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 13.3.2 receive data register (rdr) rdr is an 8-bit register that stores received da ta. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stor ed. after this, rsr is receive-enabled. as rsr and rdr function as a double buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00 by a reset, in sta ndby mode, watch mode,subactive mode, subsleep mode or module stop mode. 13.3.3 transmit data register (tdr) tdr is an 8-bit register that stores data for tran smission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double-buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during serial transmission, the sci transfers the written data to tsr to continue transmission. alt hough tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr only once after confirming that the tdre bit in ssr is set to 1. tdr is initialized to h'ff by a reset, in sta ndby mode, watch mode, subactive mode, subsleep mode or module stop mode.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 309 of 656 rej09b0071-0500 13.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. 13.3.5 serial mode register (smr) smr is used to set the sci?s serial transfer format and select the ba ud rate generator clock source. some bit functions of smr differ between norma l serial communication interface mode and smart card interface mode. ? normal serial communication interface mode (when smif in scmr is 0) bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb (bit 7) of tdr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 310 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus parity bit is even. 1: selects odd parity. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode (enabled only in asynchronous mode) when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode. for details, see 13.5, multiprocessor communication function. 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 13.3.9, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 13.3.9, bit rate register (brr)).
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 311 of 656 rej09b0071-0500 ? smart card interface mode (when smif in scmr is 1) bit bit name initial value r/w description 7 gm 0 r/w gsm mode when this bit is set to 1, the sci operates in gsm mode. in gsm mode, the timing of the tend setting is advanced by 11.0 etu (elementary time unit: the time for transfer of one bit), and clock output control mode addition is performed. for details, refer to section 13.7.8, clock output control. 0: normal smart card interface mode operation (initial value) ? the tend flag is generated 12.5 etu (11.5 etu in the block transfer mode) after the beginning of the start bit. ? clock output on/off control only 1: gsm mode operation in smart card interface mode ? the tend flag is generated 11.0 etu after the beginning of the start bit. ? in addition to clock output on/off control, high/low fixed control is supported (set using scr). 6 blk 0 r/w when this bit is set to 1, the sci operates in block transfer mode. for details on block transfer mode, refer to section 13.7.3, block transfer mode. 0: normal smart card interface mode operation (initial value) ? error signal transmission, detection, and automatic data retransmission are performed. ? the txi interrupt is generated by the tend flag. ? the tend flag is set 12.5 etu (11.0 etu in the gsm mode) after transmission starts. 1: operation in block transfer mode ? error signal transmission, detection, and automatic data retransmission are not performed. ? the txi interrupt is generated by the tdre flag. ? the tend flag is set 11.5 etu (11.0 etu in the gsm mode) after transmission starts.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 312 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. in smart card interface mode, this bit must be set to 1. 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. for details on setting this bit in smart card interface mode, refer to section 13.7.2, data format (except for block transfer mode). 3 2 bcp1 bcp0 0 0 r/w r/w basic clock pulse 0 and 1 these bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. 00: 32 clock (s = 32) 01: 64 clock (s = 64) 10: 372 clock (s = 372) 11: 256 clock (s = 256) for details, refer to section 13.7.4, receive data sampling timing and reception margin in smart card interface mode. s stands for the value of s in brr (see section 13.3.9, bit rate register (brr)). 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 13.3.9, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 13.3.9, bit rate register (brr)). note: etu (elementary time unit): abbreviation for the transfer period for one bit.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 313 of 656 rej09b0071-0500 13.3.6 serial control register (scr) scr is a register that enables or disables sci transfer operations and interrupt requests, and is also used to selection of the transfer clock source. for details on interrupt requests, refer to section 13.8, interrupt sources. some bit functions of scr differ between normal serial communication interface mode and smart card interface mode. ? normal serial communication interface mode (when smif in scmr is 0) bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. txi interrupt request cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0, or clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag in ssr, then clearing the flag to 0, or clearing the rie bit to 0. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. when this bit is cleared to 0, the transmission operation is disabled, and the tdre flag is fixed at 1.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 314 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the reception format before setting the re bit to 1. clearing the re bit to 0 does not affect the rdrf, fer,per, and orer flags, which retain their states. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 13.5, multiprocessor communication function. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rerf, fer, and orer flags in ssr, are not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting are enabled. 2 teie 0 r/w transmit end interrupt enable this bit is set to 1, tei interrupt request is enabled. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 315 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source and sck pin function. asynchronous mode 00: on-chip baud rate generator sck pin functions as i/o port 01: on-chip baud rate generator outputs a clock of the same frequency as the bit rate from the sck pin. 1x: external clock inputs a clock with a frequency 16 times the bit rate from the sck pin. clocked synchronous mode 0x: internal clock (sck pin functions as clock output) 1x: external clock (sck pin functions as clock input) legend: x: don?t care
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 316 of 656 rej09b0071-0500 ? smart card interface mode (when smif in scmr is 1) bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, txi interrupt request is enabled. txi interrupt request cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0, or clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag in ssr, then clearing the flag to 0, or clearing the rie bit to 0. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. when this bit is cleared to 0, the transmission operation is disabled, and the tdre flag is fixed at 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the reception format before setting the re bit to 1. clearing the re bit to 0 does not affect the rdrf, fer,per, and orer flags, which retain their states.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 317 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) write 0 to this bit in smart card interface mode. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rerf, fer, and orer flags in ssr, are not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting are enabled. 2 teie 0 r/w transmit end interrupt enable write 0 to this bit in smart card interface mode. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. 1 0 cke1 cke0 0 0 r/w clock enable 0 and 1 enables or disables clock output from the sck pin. the clock output can be dynamically switched in gsm mode. for details, refer to section 13.7.8, clock output control. when the gm bit in smr is 0: 00: output disabled (sck pin can be used as an i/o port pin) 01: clock output 1x: reserved when the gm bit in smr is 1: 00: output fixed low 01: clock output 10: output fixed high 11: clock output legend: x: don?t care
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 318 of 656 rej09b0071-0500 13.3.7 serial status register (ssr) ssr is a register containing stat us flags of the sci and multiproce ssor bits for transfer. 1 cannot be written to flags tdre, rdrf, orer, per, and fer; they can only be cleared. some bit functions of ssr differ between normal serial communication interface mode and smart card interface mode. ? normal serial communication interface mode (when smif in scmr is 0) bit bit name initial value r/w description 7 tdre 1 r/(w) * 1 transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt request and writes data to tdr (h8s/2268 group only) 6 rdrf 0 r/(w) * 1 receive data register full indicates that the received data is stored in rdr. [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc * 2 is activated by an rxi interrupt and transferred data from rdr (h8s/2268 group only) the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 319 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 orer 0 r/(w) * 1 overrun error indicates that an overrun error occurred during reception, causing abnormal termination. [setting condition] when the next serial reception is completed while rdrf = 1 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued either. [clearing condition] when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4 fer 0 r/(w) * 1 framing error indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. [setting condition] when the stop bit is 0 in 2 stop bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing condition] when 0 is written to fer after reading fer = 1 in 2-stop-bit mode, only the first stop bit is checked. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 320 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 per 0 r/(w) * 1 parity error indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [setting condition] when a parity error is detected during reception if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing condition] when 0 is written to per after reading per = 1 the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2 tend 1 r transmit end indicates that transmission has been ended. [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1- byte serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt request and transfer transmission data to tdr (h8s/2268 group only) 1 mpb 0 r multiprocessor bit mpb stores the multiprocessor bit in the receive data. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit data. notes: 1. only a 0 can be written to this bit, to clear the flag. 2. this bit is cleared by dtc only when disel = 0 with the transfer counter other than 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 321 of 656 rej09b0071-0500 ? smart card interface mode (when smif in scmr is 1) bit bit name initial value r/w description 7 tdre 1 r/(w) * 1 transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt request and writes data to tdr (h8s/2268 group only) 6 rdrf 0 r/(w) * 1 receive data register full indicates that the received data is stored in rdr. [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc * 2 is activated by an rxi interrupt and transferred data from rdr (h8s/2268 group only) the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 322 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 orer 0 r/(w) * 1 overrun error indicates that an overrun error occurred during reception, causing abnormal termination. [setting condition] when the next serial reception is completed while rdrf = 1 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing condition] when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4 ers 0 r/(w) * 1 error signal status indicates that the status of an error, signal 1 returned from the reception side at reception [setting condition] when the low level of the error signal is sampled [clearing condition] when 0 is written to ers after reading ers = 1 the ers flag is not affected and retains its previous state when the re bit in scr is cleared to 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 323 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 per 0 r/(w) * 1 parity error indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [setting condition] when a parity error is detected during reception if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing condition] when 0 is written to per after reading per = 1 the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 324 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to tdr. [setting conditions] ? when the te bit in scr is 0 and the ers bit is also 0 ? when the ers bit is 0 and the tdre bit is 1 after the specified interval following transmission of 1-byte data. the timing of bit setting differs according to the register setting as follows: when gm = 0 and blk = 0, 12.5 etu after transmission starts when gm = 0 and blk = 1, 11.5 etu after transmission starts when gm = 1 and blk = 0, 11.0 etu after transmission starts when gm = 1 and blk = 1, 11.0 etu after transmission starts [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc * 2 is activated by a txi interrupt and transfers transmission data to tdr (h8s/2268 group only) 1 mpb 0 r multiprocessor bit this bit is not used in smart card interface mode. 0 mpbt 0 r/w multiprocessor bit transfer write 0 to this bit in smart card interface mode. notes: 1. only a 0 can be written to this bit, to clear the flag. 2. this bit is cleared by dtc only when disel = 0 with the transfer counter other than 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 325 of 656 rej09b0071-0500 13.3.8 smart card mode register (scmr) scmr is a register that selects smart card interface mode and transfer format. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 sdir 0 r/w smart card data transfer direction selects the serial/parallel conversion format. 0: lsb-first in transfer 1: msb-first in transfer the bit setting is valid only when the transfer data format is 8 bits. for 7-bit data, lsb-first is fixed. 2 sinv 0 r/w smart card data invert specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit. to invert the parity bit, invert the o/ e bit in smr. 0: tdr contents are transmitted as they are. receive data is stored as it is in rdr 1: tdr contents are inverted before being transmitted. receive data is stored in inverted form in rdr 1 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 0 smif 0 r/w smart card interface mode select this bit is set to 1 to make the sci operate in smart card interface mode. 0: normal asynchronous mode or clocked synchronous mode 1: smart card interface mode
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 326 of 656 rej09b0071-0500 13.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rate s can be set for each channel. table 13.2 shows the relationships between the n setting in brr and bit rate b for normal asynchronous mode, clocked synchronous mode, and smart card interface mode. the initial value of brr is h'ff, and it can be read or written to by the cpu at all times. table 13.2 the relationships between th e n setting in brr and bit rate b communication mode abcs bit bit rate error 0 b = 64 2 2n-1 (n + 1) 10 6 error (%) = { b 64 2 2n-1 (n + 1) -1 } 100 10 6 asynchronous mode 1 b = 32 2 2n-1 (n + 1) 10 6 error (%) = { b 32 2 2n-1 (n + 1) -1 } 100 10 6 clocked synchronous mode ? b = 8 2 2n-1 (n + 1) 10 6 ? smart card interface mode ? b = s 2 2n+1 (n + 1) 10 6 error (%) = { b s 2 2n+1 (n + 1) -1 } 100 10 6 note: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n and s: determined by the smr settings shown in the following tables. smr setting smr setting cks1 cks0 clock source n bcp1 bcp0 s 0 0 0 0 0 32 0 1 /4 1 0 1 64 1 0 /16 2 1 0 372 1 1 /64 3 1 1 256
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 327 of 656 rej09b0071-0500 table 13.3 shows sample n settings in brr in normal asynchronous mode. table 13.4 shows the maximum bit rate for each frequency in normal asynchronous mode. table 13.6 shows sample n settings in brr in clocked synchronous mode. table 13.8 shows sample n settings in brr in smart card interface mode. in smar t card interface mode, s (the numb er of basic clock periods in a 1-bit transfer interval) can be selected. for details, refer to section 13.7.4, receive data sampling timing and reception margin . tables 13.5 and 13.7 show the maximum bit rates with external clock input. when the abcs bit in semr_0 of sci_0 is set to 1 in asynchronous mode, the maximum bit rate is twice the value shown in tables 13.4 and 13.5. table 13.3 brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 2 2.097152 2.4576 3 bit rate (bps) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.33 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 ? ? ? 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 ? ? ? ? ? ? 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 ? ? ? ? ? ? 0 2 0.00 38400 ? ? ? ? ? ? 0 1 0.00 ? ? ?
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 328 of 656 rej09b0071-0500 table 13.3 brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 3.6864 4 4.9152 5 bit rate (bps) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.33 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 2 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 1 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 ? ? ? 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 ? ? ? 0 3 0.00 0 3 1.73 operating frequency (mhz) 6 6.144 7.3728 8 bit rate (bps) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 ? ? ? 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 ? ? ?
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 329 of 656 rej09b0071-0500 table 13.3 brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 9.8304 10 12 12.288 bit rate (bps) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00 operating frequency (mhz) 14 14.7456 16 17.2032 bit rate (bps) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 ?0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 ?0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 0 16 1.20 38400 ? ? ? ? 11 0.00 0 12 0.16 0 13 0.00
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 330 of 656 rej09b0071-0500 table 13.3 brr settings for various bit rates (asynchronous mode) (4) operating frequency (mhz) 18 19.6608 20 bit rate (bps) n n error (%) n n error (%) n n error (%) 110 3 79 ?0.12 3 86 0.31 3 88 ?0.25 150 2 233 0.16 2 255 0.00 2 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 1 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 0 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 ?0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 ?1.36 31250 0 17 0.00 0 19 ?1.70 0 19 0.00 38400 0 14 ?2.34 0 15 0.00 0 15 1.73 table 13.4 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (kbps) n n (mhz) maximum bit rate (kbps) n n 2 62.5 0 0 9.8304 307.2 0 0 2.097152 65.536 0 0 10 312.5 0 0 2.4576 76.8 0 0 12 375.0 0 0 3 93.75 0 0 12.288 384.0 0 0 3.6864 115.2 0 0 14 437.5 0 0 4 125.0 0 0 14.7456 460.8 0 0 4.9152 153.6 0 0 16 500.0 0 0 5 156.25 0 0 17.2032 537.6 0 0 6 187.5 0 0 18 562.5 0 0 6.144 192.0 0 0 19.6608 614.4 0 0 7.3728 230.4 0 0 20 625.0 0 0 8 250.0 0 0
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 331 of 656 rej09b0071-0500 table 13.5 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (kbps) (mhz) external input clock (mhz) maximum bit rate (kbps) 2 0.5000 31.25 9.8304 2.4576 153.6 2.097152 0.5243 32.768 10 2.5000 156.25 2.4576 0.6144 38.4 12 3.0000 187.5 3 0.7500 46.875 12.288 3.0720 192.0 3.6864 0.9216 57.6 14 3.5000 218.75 4 1.0000 62.5 14.7456 3.6864 230.4 4.9152 1.2288 76.8 16 4.0000 250.0 5 1.2500 78.125 17.2032 4.3008 268.8 6 1.5000 93.75 18 4.5000 281.25 6.144 1.5360 96.0 19.6608 4.9152 307.2 7.3728 1.8432 115.2 20 5.0000 312.5 8 2.0000 125.0
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 332 of 656 rej09b0071-0500 table 13.6 brr settings for various bit rates (clocked synchronous mode) operating frequency (mhz) 2 4 8 10 16 20 bit rate (bps) n n n n n n n n n n n n 110 3 70 ? ? 250 2 124 2 249 3 124 ? ? 3 249 500 1 249 2 124 2 249 ? ? 3 124 ? ? 1k 1 124 1 249 2 124 ? ? 2 249 ? ? 2.5k 0 199 1 99 1 199 1 249 2 99 2 124 5k 0 99 0 199 1 99 1 124 1 199 1 249 10k 0 49 0 99 0 199 0 249 1 99 1 124 25k 0 19 0 39 0 79 0 99 0 159 0 199 50k 0 9 0 19 0 39 0 49 0 79 0 99 100k 0 4 0 9 0 19 0 24 0 39 0 49 250k 0 1 0 3 0 7 0 9 0 15 0 19 500k 0 0 * 0 1 0 3 0 4 0 7 0 9 1m 0 0 * 0 1 0 3 0 4 2.5m 0 0 * 0 1 5m 0 0 * legend: blank : cannot be set. ? : can be set, but there will be a degree of error. * : continuous transfer is not possible. table 13.7 maximum bit rate with external clock input (clocked synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bps) (mhz) external input clock (mhz) maximum bit rate (bps) 2 0.3333 0.333 12 2.0000 2.000 4 0.6667 0.667 14 2.6667 2.667 6 1.0000 1.000 16 3.0000 3.000 8 1.3333 1.333 20 3.3333 3.333 10 1.6667 1.667
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 333 of 656 rej09b0071-0500 table 13.8 examples of bit rate for variou s brr settings (smart card interface mode) (when n = 0 and s = 372) operating frequency (mhz) 5.00 7.00 7.1424 10.00 10.7136 bit rate (bps) n error (%) n error (%) n error (%) n error (%) n error (%) 6720 0 0.01 1 30 1 28.75 1 0.01 1 7.14 9600 0 30.00 0 1.99 0 0.00 1 30 1 25 operating frequency (mhz) 13.00 14.2848 16.00 18.00 20.00 bit rate (bps) n error (%) n error (%) n error (%) n error (%) n error (%) 6720 2 13.33 2 4.76 2 6.67 3 9.99 3 0.01 9600 1 8.99 1 0.00 1 12.01 2 15.99 2 6.66 table 13.9 maximum bit rate at various f requencies (smart card interface mode) (when s = 372) (mhz) maximum bit rate (bps) n n 5.00 6720 0 0 7.00 9409 0 0 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 334 of 656 rej09b0071-0500 13.3.10 serial expansion mode register (semr_0) semr_0 is an 8-bit register that expands sci_0 functions; such as setting of the basic clock, selecting of the clock source, and automatic setting of the transfer rate. bit bit name initial value r/w description 7 ? 0 r/w reserved this is a readable/writable bit, but the write value should always be 0. 6 to 4 ? all 0 ? reserved the write value should always be 0. 3 abcs 0 r/w asynchronous basic clock select selects the 1-bit-interval base clock in asynchronous mode. the abcs setting is valid in asynchronous mode (c/ a in smr = 0). 0: operates on a basic clock with a frequency of 16-times the transfer rate. 1: operates on a basic clock with a frequency of 8-times the transfer rate.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 335 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 1 0 acs2 acs1 acs0 0 0 0 r/w r/w r/w asynchronous clock source select when an average transfer rate is selected, the base clock is set automatically regardless of the abcs value. note that average transfer rates are not supported for operating frequencies other than 10.667 mhz and 16 mhz. the acs0 to acs0 settings are valid when the external clock input is selected (cke1 in scr = 1) in asynchronous mode (c/ a in smr = 0). 000: external clock input 001: selects the average transfer rate 115.152 kbps only for = 10.667mhz (operates on a basic clock with a frequency of 16-times the transfer rate). 001: selects the average transfer rate 460.606 kbps only for = 10.667mhz (operates on a basic clock with a frequency of 8-times the transfer rate). 011: reserved 100: tpu clock input (logical ands tioca1 and tioca2) 101: 115.196 kbps average transfer rate (for = 6 mhz only) is selected (sci0 operates on base clock with frequency of 16 times transfer rate) 110: 460.784 kbps average transfer rate (for = 6 mhz only) is selected (sci0 operates on base clock with frequency of 16 times transfer rate) 111: 720 kbps average transfer rate (for = 6 mhz only) is selected (sci0 operates on base clock with frequency of 8 times transfer rate) figure 13.3 and 13.4 shows an example of the internal base clock when the average transfer rate is selected.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 336 of 656 rej09b0071-0500 12345678 9 10 11 123 45 67 8 12 13 14 15 16 17 18 1 9 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 3 9 40 41 42 43 44 45 46 47 48 4 9 50 51 52 53 54 55 1 2 3 4 28 2 9 5.333 mhz 3.6848 mhz 123 123 45678 9 10 11 12 13 14 15 16 17 18 1 9 20 21 23 22 45 67 8 9 10 11 12 13 14 15 16 24 25 26 27 30 31 32 33 34 35 36 37 38 3 9 40 41 42 43 44 45 46 47 48 4 9 50 51 52 53 54 55 1 2 3 4 28 2 9 2.667 mhz 1.8424 mhz 1 bit = base clock x 16 * base clock 10.667 mhz/4 = 2.667 mhz 2.667 mhz x (38/55) = 1.8424 mhz (average) average transfer rate when = 10.667 mhz average transfer rate = 1.8424 mhz/16 = 115.152 kbps average error with 115.2kbps = - 0.043% 1 bit = base clock x 16 * base clock 10.667 mhz/2 = 5.333 mhz 5.333 mhz x (38/55) = 3.6848 mhz (average) average transfer rate when = 460.606 mhz average transfer rate = 3.6848 mhz/8 = 460.606 kbps average error with 460.6kbps = - 0.043% note: the 1-bit length changes according to the base clock synchronization. figure 13.3 example of internal base clock when average transfer rate is selected (1)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 337 of 656 rej09b0071-0500 12345678 9 10 123 45 678 11 12 13 14 15 16 17 18 1 9 20 21 23 22 24 25 1 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 25 34 8 mhz 7.3725 mhz 12345678 9 10 11 12 13 14 15 16 17 12345678 9 10 11 12 13 14 15 16 18 1 9 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 3 9 40 41 42 43 44 45 46 47 48 4 9 50 51 52 53 54 55 56 57 58 5 9 28 2 9 8 mhz 5.76 mhz 123 2 mhz 1.8431 mhz 45678 9 10 11 12 13 14 15 16 17 12345678 9 10 11 12 13 14 15 16 18 1 9 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 3 9 40 41 42 43 44 45 46 47 48 4 9 50 51 1 2 3 4 5 6 7 8 28 2 9 1 bit = base clock x 16* base clock 16 mhz/8 = 2 mhz 2 mhz x (47/51) = 1.8431 mhz (average) average transfer rate when f = 115.1 9 6 kbps average transfer rate = 1.8431 mhz/16 = 115.1 9 6 kbps average error with 115.2kbps = - 0.004% 1 bit = base clock x 16 * base clock 16 mhz/2 = 8 mhz 8 mhz x (47/51) = 7.3725 mhz (average) average transfer rate when = 460.784 kbps average transfer rate = 7.3725 mhz/16 = 460.784 kbps average error with 460.8kbps = - 0.004% 1 bit = base clock x 16 * base clock 16 mhz/2 = 8 mhz 8 mhz x (18/5) = 5.76 mhz (average) average transfer rate when = 720 kbps average transfer rate = 5.76 mhz/8 = 720 kbps average error with 720kbps = - 0% note: the 1-bit length changes according to the base clock synchronization. figure 13.4 example of internal base clock when average transfer rate is selected (2)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 338 of 656 rej09b0071-0500 13.4 operation in as ynchronous mode figure 13.5 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the tran smission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communica tion. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered struct ure, so that data can be read or written during transmission or reception, enabling continuous data transfer. in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. the sci_0 samples the data on the 4th pulse of a clock with a frequency of 8 times the length of one bit when the abcs bit in semr_0 is 1. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 13.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 13.4.1 data transfer format table 13.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, refer to section 13.5, multiprocessor communication function.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 339 of 656 rej09b0071-0500 table 13.10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 ? ? ? ? s 8-bit data stop s 7-bit data stop s 8-bit data stopstop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stopstop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 12345678 9 10 11 12 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 340 of 656 rej09b0071-0500 13.4.2 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.6. thus, the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f) | 100 [%] 1 2n | d ? 0.5 | n ... formula (1) where m: reception margin (%) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0, d (clock duty) = 0.5, and n (ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 13.6 receive data samplin g timing in asynchronous mode
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 341 of 656 rej09b0071-0500 13.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci?s serial clock, according to the setting of the c/ a bit in smr and the cke0 and cke1 bits in scr. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when an external clock is selected, a base clock with an average transfer rate can be selected by setting bits acs2 to acs0 in semr_0. when the sci is operated on an internal clock, the clock can be output from the sck pin when setting cke1 = 0 and cke0 = 1. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.7. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 sck txd figure 13.7 relationship between output clock and transfer data phase (asynchronous mode)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 342 of 656 rej09b0071-0500 13.4.4 sci initialization (asynchronous mode) before transmitting and receiving data, you should firs t clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when the external clock is used in async hronous mode, the clock must be supplied even during initialization. wait start initialization set data transfer format in smr, scmr, and semr_0 [1] set cke1 and cke0 bits in scr (te, re bits 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits * in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr, scmr and semr_0. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock or an average transfer rate clock by bits ac2 to acs0 in semr_0 is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. note: * perform this set operation with the rxd pin in the 1 state. if the re bit is set to 1 with the rxd pin in the 0 state, it may be misinterpreted as a start bit. figure 13.8 sample sci initialization flowchart
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 343 of 656 rej09b0071-0500 13.4.5 serial data transmission (asynchronous mode) figure 13.9 shows an example of operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr. if the flag is cleared to 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. continuous transmission is possibl e because the txi interru pt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 13.9 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 344 of 656 rej09b0071-0500 figure 13.10 shows a sample flowchart for data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc * is activated by a transmit data empty interrupt (txi) request, and data is written to tdr. (h8s/2268 group only) [4] break output at the end of serial transmission: to output a break in serial transmission, set dr for the port corresponding to the txd pin to 0, clear ddr to 1, then clear the te bit in scr to 0. note: * the case, in which the dtc automatically checks and clears the tdre flag, occurs only when disel in dtc is 0 with the transfer counter not being 0. therefore, the tdre flag should be cleared by cpu when disel is 1, or when disel is 0 with the transfer counter being 0. figure 13.10 sample serial transmission flowchart
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 345 of 656 rej09b0071-0500 13.4.6 serial data recepti on (asynchronous mode) figure 13.11 shows an example of operation fo r reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line. if a start bit is detected, the sci performs internal synchronization, receives receive data in rs r, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of th e next data is completed while the rdrf flag is still set to 1), the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible becau se the rxi interrupt r outine reads the receive data transferred to rdr before reception of the next receive data has been completed. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated figure 13.11 example of sci operation in reception (example with 8-bit data, parity, one stop bit)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 346 of 656 rej09b0071-0500 table 13.11 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive er ror is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive er ror flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 13.12 shows a sample flow chart for serial data reception. table 13.11 ssr status flags and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 347 of 656 rej09b0071-0500 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error processing (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer = 1 rdrf = 1 all data received? [1] sci initialization: the rxd pin is automatically designated as the receive data input pin. [2] [3] receive error processing and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. [4] sci status check and receive data read: read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. [5] serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. the rdrf flag is cleared automatically when dtc * is activated by an rxi interrupt and the rdr value is read. (h8s/2268 group only) note: * the case, in which the dtc automatically clears the rdrf flag, occurs only when disel in dtc is 0 with the transfer counter not being 0. therefore, the rdrf flag should be cleared by cpu when disel is 1, or when disel is 0 with the transfer counter being 0. figure 13.12 sample serial reception data flowchart (1)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 348 of 656 rej09b0071-0500 [3] error processing parity error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing orer = 1 fer = 1 break? per = 1 clear re bit in scr to 0 figure 13.12 sample serial reception data flowchart (2)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 349 of 656 rej09b0071-0500 13.5 multiprocessor comm unication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is performed, each receiving station is addressed by a unique id code. the serial communica tion cycle consists of two component cycles; an id transmission cycle that specifies the receiving station, and a data tr ansmission cycle. the multiprocessor bit is used to differentiate between the id transmission cy cle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 13.13 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rs r to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and orer to 1, are inhibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpb bit in ssr is set to 1 and the mpie bit is automatically cleared, t hus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 350 of 656 rej09b0071-0500 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 13.13 example of communication using multiprocessor format (transmission of data h'aa to receiving station a)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 351 of 656 rej09b0071-0500 13.5.1 multiprocessor serial data transmission figure 13.14 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and set mpbt bit in ssr no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 break output? clear tdre flag to 0 [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc * is activated by a transmit data empty interrupt (txi) request, and data is written to tdr. (h8s/2268 group only) [4] break output at the end of serial transmission: to output a break in serial transmission, set the port dr to 0, clear ddr to 1, then clear the te bit in scr to 0. note: * the case, in which the dtc automatically clears the tdre flag, occurs only when disel in dtc is 0 with the transfer counter not being 0. therefore, the tdre flag should be cleared by cpu when disel is 1, or when disel is 0 with the transfer counter being 0. figure 13.14 sample multiprocessor serial transmission flowchart
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 352 of 656 rej09b0071-0500 13.5.2 multiprocessor s erial data reception figure 13.16 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 13.15 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0d0d1 d71 1 0d0d1 d7 01 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit data (id2) start bit stop bit start bit data (data2) stop bit rxi interrupt request (multiprocessor interrupt) generated mark state (idle state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this station?s id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station?s id mpie rdr value 0d0d1 d71 1 0d0d1 d7 01 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) generated mark state (idle state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this station?s id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches station?s id data2 id1 mpie = 0 mpie = 0 figure 13.15 example of sci operation in reception (example with 8-bit data, mult iprocessor bit, one stop bit)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 353 of 656 rej09b0071-0500 yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error processing (continued on next page) [5] no yes fer orer = 1 rdrf = 1 all data received? read mpie bit in scr [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station?s id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer orer = 1 read receive data in rdr rdrf = 1 [1] sci initialization: the rxd pin is automatically designated as the receive data input pin. [2] id reception cycle: set the mpie bit in scr to 1. [3] sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station?s id, clear the rdrf flag to 0. [4] sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] receive error processing and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. figure 13.16 sample multiprocesso r serial reception flowchart (1)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 354 of 656 rej09b0071-0500 error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing orer = 1 fer = 1 break? clear re bit in scr to 0 [5] figure 13.16 sample multiprocesso r serial reception flowchart (2)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 355 of 656 rej09b0071-0500 13.6 operation in clocke d synchronous mode figure 13.17 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or receive d synchronous with clock pulses. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sc i receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. don?t care don?t care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 13.17 data format in synchronous communication (for lsb-first) 13.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of cke0 and cke1 bits in scr. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 13.6.2 sci initialization (clocked synchronous mode) before transmitting and receiving data, the te and re bits in scr should be cl eared to 0, then the sci should be initialized as described in a samp le flowchart in figure 13.18. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. wh en the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 356 of 656 rej09b0071-0500 wait start initialization set data transfer format in smr and scmr no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? set cke1 and cke0 bits in scr (te, re bits 0) [1] [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. note: in simultaneous transmit and receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. figure 13.18 sample sci initialization flowchart 13.6.3 serial data transmission (clocked synchronous mode) figure 13.19 shows an example of sci operation for transmission in clocked synchronous mode. in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if the flag is 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. continuous transmission is possible because the txi interrupt routine writes the next transmit data to tdr before transmission of the current transmit data has been completed.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 357 of 656 rej09b0071-0500 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 13.20 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (orer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. transfer direction bit 0 serial data synchronization clock 1 frame tdre tend data written to tdr and tdre flag cleared to 0 in txi interrupt service routine txi interrupt request generated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request generated tei interrupt request generated figure 13.19 sample sci transmission operation in clocked synchronous mode
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 358 of 656 rej09b0071-0500 no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc * is activated by a transmit data empty interrupt (txi) request and data is written to tdr. (h8s/2268 group only) note: * the case, in which the dtc automatically clears the tdre flag, occurs only when disel in dtc is 0 with the transfer counter not being 0. therefore, the tdre flag should be cleared by cpu when disel is 1, or when disel is 0 with the transfer counter being 0. figure 13.20 sample serial transmission flowchart
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 359 of 656 rej09b0071-0500 13.6.4 serial data reception (clocked synchronous mode) figure 13.21 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in rsr. 2. if an overrun error occurs (when reception of th e next data is completed while the rdrf flag in ssr is still set to 1), the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated, r eceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 3. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible becau se the rxi interrupt r outine reads the receive data transferred to rdr before reception of the next receive data has finished. bit 7 serial data synchronization clock 1 frame rdrf orer eri interrupt request generated by overrun error rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt rxi interrupt request generated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 13.21 example of sci operation in reception reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 13.22 shows a sample flow chart for serial data reception. an overrun error occurs or synchronous clocks are output until the re bit is cleared to 0 when an internal clock is selected a nd only receive operation is possi ble. when a transmission and reception will be carried out in a unit of one frame, be sure to carry out a dummy transmission with only one frame by the simultaneous transmit and receive operations at the same time.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 360 of 656 rej09b0071-0500 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error processing (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 rdrf = 1 all data received? read orer flag in ssr error processing overrun error processing clear orer flag in ssr to 0 [3] [1] sci initialization: the rxd pin is automatically designated as the receive data input pin. [2] [3] receive error processing: if a receive error occurs, read the orer flag in ssr, and after performing the appropriate error processing, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. [4] sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. [5] serial reception continuation procedure: to continue serial reception, before the final bit of the current frame is received, reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0 should be finished. the rdrf flag is cleared automatically when the dtc * is activated by a receive data full interrupt (rxi) request and the rdr value is read. (h8s/2268 group only) note: * the case, in which the dtc automatically clears the rdrf flag, occurs only when disel in dtc is 0 with the transfer counter not being 0. therefore, the rdrf flag should be cleared by cpu when disel is 1, or when disel is 0 with the transfer counter being 0. figure 13.22 sample s erial reception flowchart
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 361 of 656 rej09b0071-0500 13.6.5 simultaneous serial data transmission and reception (clocked synchronous mode) figure 13.23 shows a sample flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 w ith a single instruction. to switch from receive mode to simultaneous transmit and receive m ode, after checking that the sci has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (orer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 362 of 656 rej09b0071-0500 yes [1] no initialization start transmission/reception [5] error processing [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 all data received? [2] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf = 1 read orer flag in ssr [4] read rdrf flag in ssr clear te and re bits in scr to 0 [1] sci initialization: the txd pin is designated as the transmit data output pin, and the rxd pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. [3] receive error processing: if a receive error occurs, read the orer flag in ssr, and after performing the appropriate error processing, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. [4] sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. [5] serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the final bitof the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the final bit of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr and clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc * is activated by a transmit data empty interrupt (txi) request and data is written to tdr. also, the rdrf flag is cleared automatically when the dtc * is activated by a receive data full interrupt (rxi) request and the rdr value is read. (h8s/2268 group only) notes: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 by one instruction simultaneously. * the case, in which the dtc automatically clears the tdre flag or rdrf flag, occurs only when disel in the corresponding dtc transfer is 0 with the transfer counter not being 0. therefore, the corresponding flag should be cleared by cpu when disel in the corresponding dtc transfer is 1, or when disel is 0 with the transfer counter being 0. figure 13.23 sample flowchar t of simultaneous serial tr ansmit and receive operations
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 363 of 656 rej09b0071-0500 13.7 operation in smar t card interface the sci supports an ic card (smart card) interface that conforms to iso/iec 7816-3 (identification card) as a serial communication interface extension function. switching between the normal serial communication interface and the smart card interface mode is carried out by means of a register setting. 13.7.1 pin connection example figure 13.24 shows an example of connection with the smart card. in communication with an ic card, as both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected to the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. this lsi port output is used as the reset signal. txd rxd this lsi v cc i/o connected equipment ic card data line clock line reset line clk rst sck px (port) figure 13.24 schematic diagram of smart card interfa ce pin connections 13.7.2 data format (except for block transfer mode) figure 13.25 shows the transfer data format in smart card interface mode. ? one frame consists of 8-bit data plus a parity bit in asynchronous mode. ? in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 364 of 656 rej09b0071-0500 ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output start bit data bits parity bit error signal legend: ds: d0 to d7: dp: de: figure 13.25 normal smart card interface data format data transfer with other types of ic cards (direct convention and inverse convention) are performed as described in the following. ds azzazz z za a (z) (z) state d0 d1 d2 d3 d4 d5 d6 d7 dp figure 13.26 direct conv ention (sdir = sinv = o/ e = 0) with the direction convention type ic and the above sample start character, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. for the direct convention type, clear the sdir and sinv bits in scmr to 0. according to smart card regulations, clear the o/ e bit in smr to 0 to select even parity mode. ds azzaaa z aa a (z) (z) state d7 d6 d5 d4 d3 d2 d1 d0 dp figure 13.27 inverse convention (sdir = sinv = o/ e = 1)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 365 of 656 rej09b0071-0500 with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data for the above is h'3f. for the inverse convention type, set the sdir and sinv bits in scmr to 1. according to smart card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state z. in this lsi, the sinv bit inverts only data bits d0 to d7. therefore, set the o/ e bit in smr to 1 to invert the parity bit for both transmission and reception. 13.7.3 block transfer mode operation in block transfer mode is the same as that in the normal smart card interface mode, except for the following points. ? in reception, though the parity ch eck is performed, no error signal is output even if an error is detected. however, the per bit in ssr is set to 1 and must be cleared before receiving the parity bit of the next frame. ? in transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. ? in transmission, because retransmission is not pe rformed, the tend flag is set to 1, 11.5 etu after transmission start. ? as with the normal smart card interface, the ers flag indicates the error signal status, but since error signal transfer is not performe d, this flag is always cleared to 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 366 of 656 rej09b0071-0500 13.7.4 receive data sampling ti ming and reception margin in smart card interface mode an internal clock generated by the on-chip baud rate generator can only be used as a transmission/ reception clock. in this mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal asynchronous mode) as determined by bits bcp1 and bcp0. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. as shown in figure 13.28, by sampling receive data at the ri sing-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. the reception margin is given by the following formula. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f) | 100% 1 2n | d ? 0.5 | n where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5 and n = 372 in the above formula, the reception margin formula is as follows. m = (0.5 ? 1/2 372) 100% = 49.866% internal basic clock 372 clocks 186 clocks receive data (rxd) synchronization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 13.28 receive data samp ling timing in smart card mode (using clock of 372 times the transfer rate)
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 367 of 656 rej09b0071-0500 13.7.5 initialization before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. clear the te and re bits in scr to 0. 2. clear the error flags ers, per, and orer in ssr to 0. 3. set the gm, blk, o/ e , bcp0, bcp1, cks0, cks1 bits in smr. set the pe bit to 1. 4. set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. 5. set the value corresponding to the bit rate in brr. 6. set the cke0 and cke1 bits in scr. clear th e tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. to switch from receive mode to transmit mode, afte r checking that the sci has finished reception, initialize the sci, and set re to 0 and te to 1. whether sci has finished reception or not can be checked with the rdrf, per, or orer flags. to switch from transmit mode to receive mode, after checking that the sci has finished transmission, initialize the sci, and set te to 0 and re to 1. whether sci has finished transmission or not can be checked with the tend flag. 13.7.6 serial data transmission (except for block transfer mode) as data transmission in smart card interf ace mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). figure 13.29 illustrates the retransfer operation when the sci is in transmit mode. 1. if an error signal is sent back from the receiving end after transmission of one frame is complete, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the ers bit in ssr should be cleared to 0 by the time the next parity bit is sampled. 2. the tend bit in ssr is not set for a frame in which an error signal indicating an abnormality is received. data is retransferred from td r to tsr, and retransmitted automatically. 3. if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. transmission of one frame, including a retransfer, is judged to have been completed, and the
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 368 of 656 rej09b0071-0500 tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. writing transmit data to tdr transfers the next transmit data. figure 13.31 shows a flowchart for transmission. in the h8s/2268 group, a sequence of transmit operations can be performed automatically by specifying the dtc to be activated with a txi interrupt source. in a transmit operation, the tdre flag is set to 1 at the same time as the tend flag in ssr is set, and a txi interrupt will be generated if the tie bit in scr has been set to 1. if the txi request is designated beforehand as a dtc activation source, the dtc will be activated by the txi request, and transfer of the transmit data will be carried out. at this moment, when the disel bit in dtc is 0 and the transfer counter is other than 0, the tdre and tend flags are automatically cleared to 0 when data is transferred by the dtc. when the disel bit in the corresponding dtc is 1, or both disel bit and the transfer counter are 0, flags are not cleared although transfer data is written to tdr by dtc. consequently give the cpu an instruction of flag clear processing. in addition, in the event of an error, the sci retransmits the same data automatically. during this period, the tend flag remains cleared to 0 and the dtc is not activated. therefore, the sci and dtc will automatically transmit the specified number of bytes in the event of an error, in cluding retransmission. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dtc, it is essential to set and enable the dtc before carrying out sci setting. for details of the dtc setting procedures, refer to section 8, data transfer controller (dtc). d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend fer/ers transfer to tsr from tdr transfer to tsr from tdr transfer to tsr from tdr figure 13.29 retransfer operation in sci transmit mode
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 369 of 656 rej09b0071-0500 the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 13.30. ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5etu txi (tend interrupt) 11.0etu de guard time when gm = 0 when gm = 1 start bit data bits parity bit error signal legend: ds: d0 to d7: dp: de: figure 13.30 tend flag generation timing in transmission operation
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 370 of 656 rej09b0071-0500 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre flag in ssr to 0 error processing error processing tend = 1? all data transmitted ? tend = 1? ers = 0? ers = 0? figure 13.31 example of transmission processing flow
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 371 of 656 rej09b0071-0500 13.7.7 serial data r eception (except for block transfer mode) data reception in smart card interface mode uses the same operation procedure as for normal serial communication interface mode. figure 13.32 illustrates the retransfer operation when the sci is in receive mode. 1. if an error is found when the received pa rity bit is ch ecked, the per bit in ssr is automatically set to 1. if the rie bit in scr is set at this time, an eri interrupt request is generated. the per bit in ssr should be kept clear ed to 0 until the next pa rity bit is sampled. 2. the rdrf bit in ssr is not set for a frame in which an error has occurred. 3. if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1, the receive operation is judged to have been co mpleted normally, and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. figure 13.33 shows a flowchart for reception. in the h8s/2268 group, a sequence of receive operations can be performed automatically by specifying the dtc to be activated using an rxi interrupt source. in a receive operation, an rxi in terrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dtc activation source, the dtc will be activated by the rxi request, and the r eceive data will be transferred. the rdrf flag is cleared to 0 automatically when the disel bit in dtc is 0 and the transfer counter is other than 0. when the disel bit in dtc is 1, or both the disel bit and the transfer counter are 0, flag is not cleared although the receive data is transf erred by dtc. consequently, give the cpu an instruction of flag clear processing. if an error o ccurs in receive mode and the orer or per flag is set to 1, a transfer error interrupt (eri) request will be generated. hence, so the error flag must be cleared to 0. in the event of an error, the dtc is not activated and receive data is skipped. therefore, receive data is transferred for only th e specified number of bytes in the event of an error. even when a parity error o ccurs in receive mode and the per fl ag is set to 1, the data that has been received is transferred to rdr and can be read from there. note: for details on receive operations in block tran sfer mode, refer to section 13.4, operation in asynchronous mode.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 372 of 656 rej09b0071-0500 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame rdrf per figure 13.32 retransfer opera tion in sci receive mode initialization read rdr and clear rdrf flag in ssr to 0 clear re bit to 0 start reception start error processing no no no yes yes orer = 0 and per = 0 rdrf = 1? all data received? yes figure 13.33 example of reception processing flow 13.7.8 clock output control when the gm bit in smr is set to 1, the clock output level can be fixed with bits cke0 and cke1 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 13.34 shows the timing for fixing the clock output level. in this example, gm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 373 of 656 rej09b0071-0500 specified pulse width sck cke0 specified pulse width figure 13.34 timing for fixing clock output level when turning on the power or switching between smart card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. powering on: to secure clock duty from power-on, the following switching procedure should be followed. 1. the initial state is port input and high impeda nce. use a pull-up resistor or pull-down resistor to fix the potential. 2. fix the sck pin to the specified output level with the cke1 bit in scr. 3. set smr and scmr, and switch to smart card mode operation. 4. set the cke0 bit in scr to 1 to start clock output. when changing from smart card interface mode to software standby mode: 1. set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. 2. write 0 to the te bit and re bit in the seri al control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. 3. write 0 to the cke0 bit in scr to halt the clock. 4. wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. 5. make the transition to the software standby state.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 374 of 656 rej09b0071-0500 when returning to smart card interface mode from software standby mode: 1. exit the software standby state. 2. write 1 to the cke0 bit in scr and output the clock. signal generation is started with the normal duty. software standby normal operation normal operation figure 13.35 clock halt and restart procedure 13.8 interrupt sources 13.8.1 interrupts in normal serial communication interface mode table 13.12 shows the interrupt sources in no rmal serial communication interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to perform da ta transfer. the tdre flag is cleared to 0 automatically when data is transferred by the dtc. (h8s/2268 group only) when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt request can activ ate the dtc to transfer data. th e rdrf flag is cleared to 0 automatically when data is transferred by the dtc * . (h8s/2268 group only) a tei interrupt is requested when the tend flag is set to 1 and the teie bit is set to 1. if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt has priority for acceptance. however, if the tdre and tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot branch to the tei interrupt routine later. note: * flags are cleared only when th e disel bit in dtc is 0 with the transfer counter other than 0.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 375 of 656 rej09b0071-0500 table 13.12 interrupt sources of s erial communication interface mode channel name interrupt source interrupt flag dtc activation * 2 priority * 1 eri0 receive error orer, fer, per not possible high rxi0 receive data full rdrf possible txi0 transmit data empty tdre possible 0 tei0 transmission end tend not possible eri1 receive error orer, fer, per not possible rxi1 receive data full rdrf possible txi1 transmit data empty tdre possible 1 tei1 transmission end tend not possible eri2 receive error orer, fer, per not possible rxi2 receive data full rdrf possible 2 txi2 transmit data empty tdre possible tei2 transmission end tend not possible low notes: 1. indicates the initial state immediately after a reset. priorities in channels can be changed by the interrupt controller. (h8s/2268 group only) 2. supported only by the h8s/2268 group. 13.8.2 interrupts in smart card interface mode table 13.13 shows the interrupt sources in smart card interface mode. the transmit end interrupt (tei) request cannot be used in this mode. note: in case of block transfer mode, see 13.8.1, interrupts in nomal serial communication interface mode.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 376 of 656 rej09b0071-0500 table 13.13 interrupt sources in smart card interface mode channel name interrupt source interrupt flag dtc activation * 2 priority * 1 eri0 receive error, detection orer, per, ers not possible high rxi0 receive data full rdrf possible 0 txi0 transmit data empty tend possible eri1 receive error, detection orer, per, ers not possible rxi1 receive data full rdrf possible 1 txi1 transmit data empty tend possible eri2 receive error, detection orer, per, ers not possible 2 rxi2 receive data full rdrf possible txi2 transmit data empty tend possible low notes: 1. indicates the initial state immediately after a reset. priorities in channels can be changed by the interrupt controller. (h8s/2268 group only) 2. supported only by the h8s/2268 group. 13.9 usage notes 13.9.1 module stop mode setting sci operation can be disabled or enabled using the module stop control register. the initial setting is for sci operation to be halted. register acce ss is enabled by clearing module stop mode. for details, refer to section 22, power-down modes. 13.9.2 break detection and processing (asynchronous mode only) when framing error (fer) detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, setting the fer flag, and possibly the per flag. note that as the sci con tinues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 13.9.3 mark state and break detection (asynchronous mode only) when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by ddr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both ddr and dr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port,
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 377 of 656 rej09b0071-0500 and 1 is output from the txd pin. to send a break during serial transmission, first set pdr to 1 and dr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 13.9.4 receive error flags and transmit op erations (clocked sync hronous mode only) transmission cannot be started when a receive error fl ag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. 13.9.5 restrictions on use of dtc (h8s/2268 group only) ? when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after tdr is updated by the dtc. misoperation may occur if the transmit clock is input within 4 clocks after tdr is updated. (figure 13.36) ? when rdr is read by the dtc, be sure to set the activation source to the relevant sci reception data full interrupt (rxi). ? the flags are automatically clear ed to 0 by dtc during the data transfer only when the disel bit in dtc is 0 with the transfer counter other than 0. when the disel bit in the corresponding dtc is 1, or both the disel bit and the transfer counter are 0, give the cpu an instruction to clear flags. note that, particularly during transmission, the tdre flag that is not cleared by the cpu causes incorrect transmission. t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t > 4 clocks. tdre figure 13.36 example of clocked synchronous transmission by dtc
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 378 of 656 rej09b0071-0500 13.9.6 operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode, software standby mode, watch mode, su bactive mode, or subsleep mode transition. tsr, tdr, and ssr are reset. the output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted w ill be undefined. when transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr read -> tdr write -> tdre clearance. to transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 13.37 shows a sample flowchart for mode transition during transmission. port pin states are shown in figures 13.38 and 13.39. operation should also be stopped (by clearing te, tie, and teie to 0) before making a transition from transmission by dtc transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. to perform transmission with the dtc after the relevant mode is cleared, setting te and tie to 1 will set the txi flag and start dtc transmission. (h8s/2268 group only) ? reception receive operation should be stoppe d (by clearing re to 0) befo re making a module stop mode, software standby mode, watch mode, subactive mode , or subsleep mode transition. rsr, rdr, and ssr are reset. if a transition is made with out stopping operation, the data being received will be invalid. to continue receiving without changing the rece ption mode after the relevant mode is cleared, set re to 1 before starting reception. to recei ve with a different receive mode, the procedure must be started again from initialization. figure 13.40 shows a sample flowchart for mode transition during reception.
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 379 of 656 rej09b0071-0500 read tend flag in ssr te = 0 transition to software standby mode, etc. exit from software standby mode, etc. change operating mode? no all data transmitted? tend = 1 yes yes yes no no [1] [3] [2] te = 1 initialization [1] data being transmitted is interrupted. after exiting software standby mode, etc., normal cpu transmission is possible by setting te to 1, reading ssr, writing tdr, and clearing tdre to 0, but note that if the dtc has been activated, the remaining data in dtcram will be transmitted when te and tie are set to 1. (h8s/2268 group only) [2] if tie and teie are set to 1, clear them to 0 in the same way. [3] includes module stop mode, watch mode, subactive mode, and subsleep mode. figure 13.37 sample flowchart for mode transition during transmission sck output pin te bit txd output pin port input/output high output port input/output high output start stop start of transmission end of transmission port input/output sci txd output port sci txd output port transition to software standby exit from software standby figure 13.38 asynchronous transmission using internal clock
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 380 of 656 rej09b0071-0500 port input/output last txd bit held high output * port input/output marking output port input/output sci txd output port port note: * initialized by software standby. sck output pin te bit txd output pin sci txd output start of transmission end of transmission transition to software standby exit from software standby figure 13.39 synchronous transmission using internal clock re = 0 transition to software standby mode, etc. read receive data in rdr read rdrf flag in ssr exit from software standby mode, etc. change operating mode? no rdrf = 1 yes yes no [1] [2] re = 1 initialization [1] receive data being received becomes invalid. [2] includes module stop mode, watch mode, subactive mode, and subsleep mode. figure 13.40 sample fl owchart for mode transi tion during reception
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 381 of 656 rej09b0071-0500 13.9.7 switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 13.41) sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3. c/ a = 0 2. te = 0 half-cycle low-level output figure 13.41 operation when switching from sck pin function to port pin function
section 13 serial communication interface (sci) rev. 5.00 sep. 01, 2009 page 382 of 656 rej09b0071-0500 ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/por t pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0 sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 3. cke1 = 1 5. cke1 = 0 4. c/ a = 0 2. te = 0 high-level output figure 13.42 operation when switching from sck pin function to port pin function (example of preventing low-level output) 13.9.8 assignment and selection of registers some serial communication interface registers are a ssigned to the same address as other registers. register selection is performed by means of the iice bit in the serial control register (scrx). for details on register addresses, see section 24, list of registers.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 383 of 656 rej09b0071-0500 section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) an i 2 c bus interface is available as an option in h8s/2264 group. observe the following note when using this option. ? for mask-rom versions, a w is added to the part number in products in which this optional function is used. examples: hd6432264wtf the h8s/2268 group has an internal i 2 c bus interface of two channels, while the h8s/2264 group has that of one channel. the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register c onfiguration that controls the i 2 c bus differs partly from the philips configuration, however. the i 2 c bus interface data transfer is performed using a data line (sda) and a clock line (scl) for each channel, which allows efficient use of connectors and the area of the pcb. 14.1 features ? selection of i 2 c bus format or clocked synchronous serial format ? i 2 c bus format: addressing format with acknowledge bit, for master/slave operation ? clocked synchronous serial format: non-addressing format without acknowledge bit, for master operation only i 2 c bus format ? two ways of setting slave address ? start and stop conditions generated automatically in master mode ? selection of acknowledge out put levels when receiving ? automatic loading of acknow ledge bit when transmitting ? wait function in master mode a wait can be inserted by driving the sc l pin low after data transfer, excluding acknowledgement. the wait can be cleared by clearing the interrupt flag. ? wait function in slave mode a wait request can be generated by driving the scl pin low after data transfer, excluding acknowledgement. the wait request is cleared when the next transfer becomes possible. iicic05b_000020020700
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 384 of 656 rej09b0071-0500 ? interrupt sources ? data transfer end (including transmission mode transition with i 2 c bus format and address reception after loss of master arbitration) ? address match: when any slave address matche s or the general call address is received in slave receive mode ? start condition detection (in master mode) ? stop condition detection (in slave mode) ? selection of 16 internal clocks (in master mode) ? direct bus drive ? two pins, p35/scl0 and p34/sda0, function as nmos open-drain outputs when the bus drive function is selected. ? two pins ? p33/scl1 and p32/sda1?function as nmos-only outputs when the bus drive function is selected. (h8s/2268 group only) figure 14.1 shows a block diagram of the i 2 c bus interface. figure 14.2 shows an example of i/o pin connections to external circuits. channel i/o pins are nmos open drains, and it is possible to apply voltages in excess of the power supply (vcc) voltage for this lsi. set the upper limit of voltage applied to the power supply (vcc) power supply range +0.3 v, i.e. 5.8 v. channel 1 (h8s/2268 group only) i/o pins are driven solely by nmos, so in terms of appearance they carry out the same operations as an nmos open drain. however, the voltage which can be applied to the i/o pins depends on the voltage of the power supply (vcc) of this lsi.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 385 of 656 rej09b0071-0500 ps noise canceler noise canceler clock control bus state decision circuit arbitration decision circuit output data control circuit address comparator sar, sarx interrupt generator icdrs icdrr icdrt icsr icmr iccr internal data bus interrupt request scl sda legend: iccr: icmr: icsr: icdr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register second slave address register prescaler figure 14.1 block diagram of i 2 c bus interface
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 386 of 656 rej09b0071-0500 scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) this lsi scl sda v dd v cc scl sda figure 14.2 i 2 c bus interface connections (example: this lsi as master) 14.2 input/output pins table 14.1 shows the pin configuration for the i 2 c bus interface. table 14.1 pin configuration name abbreviation * 1 i/o function serial clock scl0 i/o iic_0 serial clock input/output serial data sda0 i/o iic_0 serial data input/output serial clock * 2 scl1 i/o iic_1 serial clock input/output serial data * 2 sda1 i/o iic_1 serial data input/output notes: 1. in the text, the channel subscript is omitted, and only scl and sda are used. 2. supported only by the h8s/2268 group.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 387 of 656 rej09b0071-0500 14.3 register descriptions the i 2 c bus interface has the following registers. registers icdr and sarx and registers icmr and sar are allocated to the same addresses. a ccessible addresses differ depending on the ice bit in iccr. sar and sarx are accessed when ice is 0, and icmr and icdr are accessed when ice is 1. for details on the module stop control register, refer to section 22.1.2, module stop control registers a to d (mstpcra to mstpcrd). ? i 2 c bus data register_0 (icdr_0) * 2 ? slave address register_0 (sar_0) * 2 ? second slave address register_0 (sarx_0) * 2 ? i 2 c bus mode register_0 (icmr_0) * 2 ? i 2 c bus control register_0 (iccr_0) * 2 ? i 2 c bus status register_0 (icsr_0) * 2 ? i 2 c bus data register_1 (icdr_1) * 1 * 2 ? slave address register_1 (sar_1) * 1 * 2 ? second slave address register_1 (sarx_1) * 1 * 2 ? i 2 c bus mode register_1 (icmr_1) * 1 * 2 ? i 2 c bus control register_1 (iccr_1) * 1 * 2 ? i 2 c bus status register_1 (icsr_1) * 1 * 2 ? ddc switch register (ddcswr) ? serial control register x (scrx) notes: 1. supported only by the h8s/2268 group. 2. some of the registers in the i 2 c bus interface are allocated to the same addresses of other registers. the iice bit in serial c ontrol register x (scrx) selects each register.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 388 of 656 rej09b0071-0500 14.3.1 i 2 c bus data register (icdr) icdr is an 8-bit readable/writable register th at is used as a transmit data register when transmitting and a receive data register when recei ving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and tr ansmit buffer (icdrt). data transfers among the three registers are performed automatically in co ordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. when tdre is 1 and the transmit buffer is empty, tdre shows that the next transmit data can be written from the cpu. when rdrf is 1, it shows that the valid receive data is stored in the receive buffer. if i 2 c is in transmit mode and the next data is in icdrt (the tdre flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if i 2 c is in receive mode and no previous data remains in icdrr (the rdrf flag is 0) following transmission/ reception of one frame of data using icdrs, data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when ml s = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset. the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 389 of 656 rej09b0071-0500 bit bit name initial value r/w description ? tdre ? ? transmit data register empty [setting conditions] ? in transmit mode, when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected ? when data is transferred from icdrt to icdrs ? when a switch is made from receive mode to transmit mode after detection of a start condition [clearing conditions] ? when transmit data is written in icdr in transmit mode ? when a stop condition is detected in the bus line state after a stop condition is issued with the i 2 c bus format or serial format selected ? when a stop condition is detected with the i 2 c bus format selected ? in receive mode ? rdrf ? ? receive data register full [setting condition] when data is transferred from icdrs to icdrr [clearing condition] when icdr (icdrr) receive dat a is read in receive mode
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 390 of 656 rej09b0071-0500 14.3.2 slave address register (sar) sar selects the slave address and selects the transfer format. sar can be written and read only when the ice bit is cleared to 0 in iccr. bit bit name initial value r/w description 7 6 5 4 3 2 1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w slave address 6 to 0 sets a slave address 0 fs 0 r/w selects the transfer format together with the fsx bit in sarx. refer to table 14.2. 14.3.3 second slave address register (sarx) sarx stores the second slave address and select s the transfer format. sarx can be written and read only when the ice bit is cleared to 0 in iccr. bit bit name initial value r/w description 7 6 5 4 3 2 1 svax6 svax5 svax4 svax3 svax2 svax1 svax0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w slave address 6 to 0 sets the second slave address 0 fsx 1 r/w selects the transfer format together with the fs bit in sar. refer to table 14.2.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 391 of 656 rej09b0071-0500 table 14.2 transfer format sar sarx fs fsx i 2 c transfer format 0 0 sar and sarx are used as the slave addresses with the i 2 c bus format. 0 1 only sar is used as the slave address with the i 2 c bus format. 1 0 only sarx is used as the slave address with the i 2 c bus format. 1 1 clock synchronous serial format (sar and sarx are invalid) 14.3.4 i 2 c bus mode register (icmr) icmr sets the transfer format and transfer rate. it can only be accessed when the ice bit in iccr is 1. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 wait 0 r/w wait insertion bit this bit is valid only in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 392 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w serial clock select 2 to 0 this bit is valid only in master mode. these bits select the required transfer rate, together with the iicx 1 and iicx0 bit in scrx. refer table 14.3. 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. i 2 c bus format clocked synchronous mode 000: 9 bit 000: 8 bit 001: 2 bit 001: 1 bit 010: 3 bit 010: 2 bit 011: 4 bit 011: 3 bit 100: 5 bit 100: 4 bit 101: 6 bit 101: 5 bit 110: 7 bit 110: 6 bit 111: 8 bit 111: 7 bit
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 393 of 656 rej09b0071-0500 table 14.3 i 2 c transfer rate scrx icmr bit 5 or 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 0 0 0 /28 179 mhz 286 khz 357 khz 571 khz * 714 khz * 0 0 0 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz * 0 0 1 0 /48 104 khz 167 khz 208 khz 333 khz 417 khz * 0 0 1 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 0 1 0 0 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 1 0 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 0 1 1 0 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 0 1 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 0 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 1 0 0 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 0 1 0 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 1 0 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 1 0 0 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 1 1 0 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 1 1 1 0 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 1 1 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz note: * out of the range of the i 2 c bus interface specification (normal mode: 100 khz in max. and high-speed mode: 400 khz in max)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 394 of 656 rej09b0071-0500 14.3.5 serial control register x (scrx) scrx controls the iic operating modes. bit bit name initial value r/w description 7 ? 0 r/w reserved the initial value should not be changed. 6 5 iicx1 * iicx0 0 0 r/w r/w i 2 c transfer rate select 1 and 0 selects the transfer rate in master mode, together with bits cks2 to cks0 in icmr. refer to table 14.3. iicx1 controls iic_1 and iicx0 controls iic_0. note: * in the h8s/2264 group, this bit is reserved. the initial value should not be changed. 4 iice 0 r/w i 2 c master enable controls cpu access to the iic data register and control registers (iccr, icsr, icdr/sarx, and icmr/sar). 0: cpu access to the iic data register and control registers is disabled. 1: cpu access to the iic data register and control registers is enabled. 3 flshe 0 r/w for details on this bit, refer to section 20.5.7, serial control register x (scrx). 2 to 0 ? all 0 r/w reserved the initial value should not be changed.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 395 of 656 rej09b0071-0500 14.3.6 i 2 c bus control register (iccr) i 2 c bus control register (iccr) consists of the control bits and interrupt request flags of i 2 c bus interface. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable when this bit is set to 1, the i 2 c bus interface module is enabled to send/receive data and drive the bus since it is connected to the scl and sda pins. icmr and icdr can be accessed. when this bit is cleared, the module is halted and separated from the scl and sda pins. sar and sarx can be accessed. 6 ieic 0 r/w i 2 c bus interface interrupt enable when this bit is 1, interrupts are enabled by iric. 5 4 mst trs 0 0 r/w master/slave select transmit/receive select 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode both these bits will be cleared by hardware when they lose in a bus contention in master mode of the i 2 c bus format. in slave receive mode, the r/ w bit in the first frame immediately after the start automatically sets these bits in receive mode or transmit mode by using hardware. the settings can be made again for the bits that were set/cleared by hardware, by reading these bits. when the trs bit is intended to change during a transfer, the bit will not be switched until the frame transfer is completed, including acknowledgement.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 396 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 acke 0 r/w acknowledge bit judgement selection 0: the value of the acknowledge bit is ignored, and continuous transfer is performed. the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. 1: if the acknowledge bit is 1, continuous transfer is interrupted. in the h8s/2268 group, the dtc * can be used to perform continuous transfer. the dtc * is activated when the irtr interrupt flag is set to 1 (irtr us one of two interrupt flags, the other being iric). when the acke bit is 0, the tdre, iric, a nd irtr flags are set on completion of data transmission, regardless of the acknowledge bit. when the acke bit is 1, the tdre, iric, and irtr flags are set on completion of data transmission when the acknowledge bit is 0, and the iric flag alone is set on completion of data transmission when the acknowledge bit is 1. when the dtc * is activated, the tdre, iric, and irtr flags are cleared to 0 after the specified number of data transfers have been executed. consequently, interrupts are not generated during continuos data transfer, but if data transmission is completed with a 1 acknowledge bit when the acke bit is set to 1, the dtc * is not activated and an interrupt is generated, if enabled. depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. note: * supported only by the h8s/2268 group.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 397 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 bbsy 0 r/w bus busy in slave mode, reading the bbsy flag enables to confirm whether the i 2 c bus is occupied or released. the bbsy flag is set to 0 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. the bbsy flag is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assuming that the start condition has been issued. writing to the bbsy flag in slave mode is disabled. in master mode, the bbsy flag is used to issue start and stop conditions. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re- transmitting a start condition. to issue a start/stop condition, use the mov instruction. the i 2 c bus interface must be set in master transmit mode before the issue of a start condition.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 398 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 iric 0 r/w i 2 c bus interface interrupt request flag also see table 14.4. [setting conditions] in i 2 c bus format master mode ? when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) ? when a wait is inserted between the data and acknowledge bit when wait = 1 ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a slave address is received after bus arbitration is lost (when the al flag is set to1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) in i 2 c bus format slave mode ? when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when the general call address (one frame including a r/w bit is h'00) is detected (when the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? when a stop condition is detected (when the stop or estp flag is set to 1) with clocked synchronous serial format ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a start condition is detected with serial format selected when a condition occurs in which internal flag of tdre and rdfr is set to 1 except for the above [clearing condition] when 0 is written in iric after reading iric = 1 when icdr is read/written by dtc (h8s/2268 group only) (when tdre or rdrf flag is cleared to 0) (as it might not be a condition to clear, for details, see section 14.4.8.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 399 of 656 rej09b0071-0500 bit bit name initial value r/w description 0 scp 1 w start condition/stop condition prohibit bit the scp bit controls the issue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. data is not stored even if it is written. when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is needed at the end of a transfer. when the tdre or rdrf internal flag is set, th e readable irtr flag may or may not be set. in the h8s/2268 group, even when data transfer is complete, the dtc activation request flag, irtr, is not set until a retransmission start condition or stop condition is detected after a slave address (sva) or general call address matched in the i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. for a continuous transfer using the dtc in the h8s/2268 group, the iric or irtr flag is not cleared at the completion of the specified number of times of transfers. on the other hand, the tdre and rdrf flags are cleared because the specifi ed number of times of read/write operations have been complete. table 14.4 shows the relationship between the flags and the transfer states.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 400 of 656 rej09b0071-0500 table 14.4 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/0 1/0 0 0 0 0 0 0 0 0 0 idle state (flag clearing required) 1 1 0 0 0 0 0 0 0 0 0 start condition issuance 1 1 1 0 0 1 0 0 0 0 0 start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 master mode wait 1 1/0 1 0 0 1 0 0 0 0 0/1 master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 arbitration lost 0 0 1 0 0 0 0 0 1 0 0 sar match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 general call address match 0 0 1 0 0 0 1 0 0 0 0 sarx match 0 1/0 1 0 0 0 0 0 0 0 0/1 slave mode transmit/receive end(except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end(after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 stop condition detected
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 401 of 656 rej09b0071-0500 14.3.7 i 2 c bus status register (icsr) icsr consists of status flags. bit bit name initial value r/w description 7 estp 0 r/(w) * error stop condition detection flag this bit is valid in i 2 c bus format slave mode. [setting condition] when a stop condition is detected during frame transfer. [clearing conditions] ? when 0 is written in estp after reading the state of 1 ? when the iric flag is cleared to 0 6 stop 0 r/(w) * normal stop condition detection flag this bit is valid in i 2 c bus format slave mode. [setting condition] when a stop condition is detected during frame transfer. [clearing conditions] ? when 0 is written in stop after reading stop = 1 ? when the iric flag is cleared to 0 5 irtr 0 r/(w) * i 2 c bus interface continuous transmission/reception interrupt request flag [setting conditions] in i 2 c bus interface slave mode ? when the tdre or rdrf flag is set to 1 when aasx = 1 in i 2 c bus interface other modes ? when the tdre or rdrf flag is set to 1 [clearing conditions] ? when 0 is written in irtr after reading irtr = 1 ? when the iric flag is cleared to 0 while ice is 1
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 402 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 aasx 0 r/(w) * second slave address recognition flag [setting condition] when the second slave address is detected in slave receive mode and fsx = 0 [clearing conditions] ? when 0 is written in aasx after reading aasx = 1 ? when a start condition is detected ? in master mode 3 al 0 r/(w) * arbitration lost flag indicates that bus arbitration was lost in master mode. [setting condition] ? when the internal sda and sda pin do not match at the rise of scl. ? when the internal scl is high at the fall of scl. [clearing conditions] ? when 0 is written in al after reading al = 1 ? when icdr data is written (transmit mode) or read (receive mode) 2 aas 0 r/(w) * slave address recognition flag [setting condition] when the slave address or general call address (one frame including a r/ w bit is h'00) is detected in slave receive mode and fs = 0. [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in aas after reading aas = 1 ? in master mode
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 403 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 adz 0 r/(w) * general call address recognition flag in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). [setting condition] when the general call address (one frame including a r/ w bit is h'00) is detected in slave receive mode and fsx = 0 or fs = 0. [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in adz after reading adz = 1 ? in master mode if a general call address is detected while fs = 1 and fsx = 0, the adz flag is set to 1; however, the general call address is not recognized (aas flag is not set to 1).
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 404 of 656 rej09b0071-0500 bit bit name initial value r/w description 0 ackb 0 r/w acknowledge bit stores acknowledge data. transmit mode: [setting condition] when 1 is received as the acknowledge bit when acke = 1 in trasmit mode. [clearing conditions] ? when 0 is received as the acknowledge bit when acke = 1 in transmit mode ? when 0 is written to the acke bit receive mode: 0: returns 0 as acknowledge data after data reception 1: retruns 1 as acknowledge data after data reception when this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when trs = 1). in reception (when trs = 0), the value set by internal software is read. when this bit is written, acknowledge data that is returned after receiving is written regardless of the trs value. if bit in icsr is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ackb bit reading value. write the acke bit to 0 to clear the ackb flag to 0, bofore transmission is ended and a stop condition is issued in master mode, or before transmission is ended and sda is released to issue a stop condition by a master device. note: * only a 0 can be written to this bit, to clear the flag.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 405 of 656 rej09b0071-0500 14.3.8 ddc switch register (ddcswr) ddcswr controls the i 2 c bus interface format automatic sw itching function and internal latch clear. bit bit name initial value r/w description 7 to 4 ? all 0 r/(w) * 1 reserved the write value should always be 0. 3 2 1 0 clr3 clr2 clr1 clr0 1 1 1 1 w w w w i 2 c bus interface clear 3 to 0: when bits clr3 to clr0 are set, a clear signal is generated for the i 2 c bus interface internal latch circuit, and the internal state is initialized. the write data for these bits is not retained. to perform i 2 c clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. 00xx: setting prohibited 0100: setting prohibited 0101: iic_0 internal latch cleared 0110: iic_1 * 2 internal iatch cleared 0111: iic_0, iic_1 * 2 internal iatch cleared 1xxx: invalid setting legend: x: don?t care notes: 1. only 0 can be written to these bits. 2. supported only by the h8s/2268 group.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 406 of 656 rej09b0071-0500 14.4 operation the i 2 c bus interface has clocked synchronous serial and i 2 c bus formats. 14.4.1 i 2 c bus data format the i 2 c bus formats are addressing formats and an ack nowledge bit is inserted. the first frame following a start condition always consists of 8 bits. the i 2 c bus format is shown in figure 14.3. the clocked synchronous serial format is a non-addressing format with no acknowledge bit. this is shown in figure 14.4. figure 14.5 shows the i 2 c bus timing. s sla r/ w a data a a/ a p 1111 n 7 1 m (a) i 2 c bus format (fs = 0 or fsx = 0) (b) i 2 c bus format (start condition retransmission, fs = 0 or fsx = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 111 n1 7 1 m1 s sla r/ w a data a/ a p 111 n2 7 1 m2 11 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 14.3 i 2 c bus data formats (i 2 c bus formats) s data data p 11 n 8 1 m fs = 1 and fsx = 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) figure 14.4 i 2 c bus data format (clocked synchronous serial format)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 407 of 656 rej09b0071-0500 sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 8 9 1-7 8 9 a data p a/ a legend: s: start condition. the master device drives sda from high to low while scl is high sla: slave address r/ w : indicates the direction of data transfer: from the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0 a: acknowledge. the receiving device drives sda low to acknowledge a transfer. data: transferred data p: stop condition. the master device drives sda from low to high while scl is high figure 14.5 i 2 c bus timing
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 408 of 656 rej09b0071-0500 14.4.2 initial setting at startup the following procedure is used to initialize the iic. clear module stop. start initialization set iice = 1 (scrx) set ice = 0 (iccr) set sar and sarx set ice = 1 (iccr) set icsr set scrx set icmr set iccr set mstpb4 = 0 (iic0) mstpb3 = 0 (iic1) (mstpcrb) enable cpu access by iic control register and data register. enable sar and sarx access. set transfer format for 1st slave address, 2nd slave address, and iic (sva8 to sva0, fs, svax6 to svax0, fsx). enable imcr and imdr access. use scl and sda pins is iic port. set acknowledge bit (ackb). set transfer rate (iicx). set transfer format, wait insertion, and transfer rate (mls, wait, cks2 to cks0). set interrupt enable, transfer mode, and acknowledge judgment (ieic, mst, trs, acke). transmit/receive start note: setting only valid for h8s/2268 group. for the h8s/2264 group, only write 1 to this bit. figure 14.6 flowchart for iic initialization (example) note: the icmr register should be written to onl y after transmit or receive operations have completed. writing to the icmr register while a transmit or receive operation is in progress could cause an erroneous value to be written to bit counter bits bc2 to bc0. this could result in improper operation. 14.4.3 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. figure 14.7 is a flowchart showing an example of the master transmit mode.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 409 of 656 rej09b0071-0500 start initial settings write bbsy = 1 and scp = 0 (iccr) bbsy = 0? yes yes yes yes yes yes yes no no no [1] initial settings. [2] determine status of scl and sda lines. [3] set to master transmit mode. [4] generate start condition. [5] wait for start condition to be met. [6] set 1st byte (slave address + r/ w ) transmit data. (perform icdr write and iric flag clear operations continuously.) [7] wait for end of 1 byte transmission. [8] judge acknowledge signal from specified. slave device. [ 9 ] set transmit data for 2nd byte onward. (perform icdr write and iric flag clear operations continuously.) [10] wait for end of 1 byte transmission. [11] judge end of transmission. [12] generate stop condition. set mst = 1 and trs = 1 (iccr) read iric flag in iccr read iric flag in iccr clear iric flag in iccr write transmit data to icdr read bbsy flag in iccr read ackb bit in icsr iric = 1? no no no iric = 1? transmit mode? ackb = 0? clear iric flag in iccr write transmit data to icdr read iric flag in iccr read ackb bit in icsr clear iric flag in iccr transmit complete? (ackb = 1?) no iric = 1? write bbsy = 0 and scp = 0 (iccr) write acke = 0 (iccr) (clear ackb = 0) end master receive mode figure 14.7 flowchart for master transmit mode (example)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 410 of 656 rej09b0071-0500 the transmission procedure and operations synchronized with the icdr writing are described below. 1. perform initial settings as described in section 14.4.2, initial setting. 2. read the bbsy flag in iccr to confirm that the bus is free. 3. set bits mst and trs to 1 in iccr to select master transmit mode. 4. write 1 to bbsy and 0 to scp. this changes sda from high to low when scl is high, and generates the start condition. 5. then iric and irtr flags are set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. 6. after the start condition is detected, write the data (slave address + r/w) to icdr. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-b it slave address and transmit/receive direction (r/ w ). as indicating the end of the transfer, and so the iric flag is cleared to 0. after writing icdr, clear iric continuously not to execute other interrupt handling routine. if one frame of data has been transmitted before the iric clearing, it can not be determine the end of transmission. the master device sequentially sends the transmission clock and the data written to icdr using the timing shown in figure 14.8. the selected slave device (i.e. the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. 7. when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. read the ackb bit in icsr to confirm that ackb is cleared to 0. when the slave device has not acknowledged (ackb bit is 1), operate the step [12] to end transmission, and retry the transmit operation. 9. write the transmit data to icdr. as indicating the end of the transfer, and so the iric flag is cleared to 0. perform the icdr write and the iric flag clearing sequentially, just as in point 6 in this flowchart. transmission of the next frame is performed in synchronization with the internal clock. 10. when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. read the ackb bit in icsr. confirm that the slave device has been acknowledged (ackb bit is 0). when there is data to be transmitted, go to the step [9] to continue next transmission. when the slave device has not acknowledged (ackb bit is set to 1), operate the step [12] to end transmission.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 411 of 656 rej09b0071-0500 12. clear the iric flag to 0. write 0 to acke in iccr, to clear received ackb contents to 0. write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. 1 [5] r/ w [7] a 2345678 9 12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 data 1 data 1 data 1 slave address start condition generated interrupt request interrupt request address + r/ w address + r/ w [ 9 ] iric clearance [ 9 ] icdr write [6] iric clearance [6] icdr write [4] write bbsy = 1 and scp = 0 (start condition issued) scl (master output) sda (master output) sda (slave output) iric irtr icdrt icdrs user processing note: do not write data to icdr. figure 14.8 example of master transmit mode operation timing (mls = wait = 0)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 412 of 656 rej09b0071-0500 [7] [10] a a 12345678 9 stop condition generated 8 9 scl (master output) sda (master output) sda (slave output) iric irtr icdr bit 7 bit 0 bit 6 data 2 data 2 data 1 data 1 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [12] write bbsy = 0 and scp = 0 (stop condition issued) [12] iric clearance [11] ackb read [ 9 ] iric clearance [ 9 ] icdr write user processing figure 14.9 example of master transmit mode stop condition generation timing (mls = wait = 0) 14.4.4 master receive operation in i 2 c bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. the master device transmits the data containing the slave address + r/ w (0: read) in the 1st frame after a start condition is generated in the master transmit mode. after the slave device is selected the switch to receive operation takes place. (1) receive operation using wait states figures 14.10 and 14.11 are flowcharts showing ex amples of the master receive mode (wait = 1).
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 413 of 656 rej09b0071-0500 set wait = 1 (icmr) clear iric flag in iccr set ackb = 0 (icsr) set trs = 0 (iccr) read icdr clear iric flag in iccr read iric flag in iccr irtr = 1? iric = 1? no no yes yes no yes yes no yes no [1] set to receive mode. [2] receive start, dummy read. [5] read receive data. [6] clear iric flag (cancel wait state). [7] set acknowledge data for final receive. [8] wait time until trs setting. [ 9 ] set trs to generate stop condition. [10] read receive data. [14] clear iric flag (cancel wait state). [16] read final receive data. [15] cancel wait mode clear iric flag. (iric flag should be cleared when wait = 0.) [17] generate stop condition. [13] data receive completed judgment. [12] receive wait state (iric set at falling edge of 8th clock cycle) or wait for end of reception of 1 byte (iric set at rising edge of 9 th clock cycle). [3] receive wait state (iric set at falling edge of 8th clock cycle) or wait for end of reception of 1 byte (iric set at rising edge of 9 th clock cycle). [4] data receive completed judgment. is next receive the last one? read icdr read icdr [11] clear iric flag (cancel wait state). clear iric flag in iccr set ackb = 1 (icsr) 1 clock cycle wait state set trs = 1 (iccr) read iric flag in iccr clear iric flag in iccr set wait = 0 (icmr) clear iric flag in iccr read icdr irtr = 1? iric = 1? write bbsy = 0 and scp = 0 (iccr) end master receive mode figure 14.10 flowchart for master receive mode (receiving multiple bytes) (wait = 1) (example)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 414 of 656 rej09b0071-0500 set wait = 1 (icmr) clear iric flag in iccr set ackb = 0 (icsr) set trs = 0 (iccr) read icdr read iric flag in iccr iric = 1? no yes yes no [1] set to receive mode [2] receive start, dummy read. [7] set acknowledge data for final receive. [ 9 ] set trs to generate stop condition. [11] clear iric flag (cancel wait state). [16] read final receive data. [15] cancel wait mode clear iric flag. (iric flag should be cleared when wait = 0.) [17] generate stop condition. [12] wait for end of reception of 1 byte. (iric set at rising edge of 9 th clock cycle) clear iric flag in iccr set ackb = 1 (icsr) set trs = 1 (iccr) read iric flag in iccr set wait = 0 (icmr) clear iric flag in iccr read icdr iric = 1? write bbsy = 0 and scp = 0 (iccr) end master receive mode [3] receive wait state (iric set at falling edge of 8th clock cycle) figure 14.11 flowchart for master recei ve mode (receiving 1 byte) (wait = 1) (example) the procedure for receiving data sequentially , using the wait states (wait bit) for synchronization with icdr (icdrr) read operations, is described below. the procedure below describes the operation for receiving multiple bytes. note that some of the steps are omitted when receiving only 1 byte. refer to figure 14.11 for details.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 415 of 656 rej09b0071-0500 [1] clear the trs bit in iccr to 0 to switch from transmit mo de to receive mode. clear the ackb bit in icsr to 0 (acknowledge data setting). clear the iric flag to 0, then set the wait bit in icmr to 1. [2] when icdr is read (dummy da ta read), reception is started, and the receive clock is output, and data received, in synchroni zation with the internal clock. [3] the iric flag is set to 1 by the following two conditions. at that point, an interrupt request is issued to the cpu if the ieic bit in iccr is set to 1. (1) the flag is set at the falling edge of the 8t h clock cycle of the recei ve clock for 1 frame. scl is automatically held low, in synchronization with the internal clock, until the iric flag is cleared. (2) the flag is set at the rising edge of the 9t h clock cycle of the recei ve clock for 1 frame. the irtr flag is set to 1, indicating that reception of 1 frame of data has ended. the master device continues to output the receive clock for the receive data. [4] read the irtr flag in icsr. if the irtr flag value is 0, the wait state is cancelled by clearing the iric flag as described in step [6] below. if the irtr flag value is 1 and the next receive data is the final receive data, perform the end processing described in step [7] below. [5] if the irtr flag value is 1, read the icdr receive data. [6] clear the iric flag to 0. the reading of the icdr flag described in step [5] and the clearing of the iric flag to 0 should be performed consecutively, with no interrupt processing occurring between them. during wait operation, clear the iric flag to 0 when the value of counter bc2 to bc0 is 2 or greater. if the iric flag is cleared to 0 when the value of counter bc2 to bc0 is 1 or 0, it will not be possible to determine when the transfer has completed. if condition [3]-1 is true, the master device drives sda to low level and returns an acknowledge signal when the receive clock outputs the 9t h clock cycle. further data can be received by repeating steps [3] through [6]. [7] set the ackb bit in icsr to 1 to set the acknowledge data for the final receive. [8] wait for at least 1 clock cycle after the iric fl ag is set to 1 and then wait for the rising edge of the 1st clock cycle of the next receive data. [9] set the tsr bit in iccr to 1 to switch from the receive mode to the transmit mode. the tsr bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle is input. [10] read the icdr receive data. [11] clear the iric flag to 0. as in step [6], read the icdr flag and clear the iric flag to 0 consecutively, with no interrupt processing occurring between them. during wait operation, clear the iric flag to 0 when the value of counter bc2 to bc0 is 2 or greater.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 416 of 656 rej09b0071-0500 [12] the iric flag is set to 1 by the following two conditions. (1) the flag is set at the falling edge of the 8th clock cycle of the r eceive clock for 1 frame. scl is automatically held low, in synchronization with the internal clock, until the iric flag is cleared. (2) the flag is set at the rising edge of the 9t h clock cycle of the recei ve clock for 1 frame. the irtr flag is set to 1, indicating that reception of 1 frame of data has ended. the master device continues to output the receive clock for the receive data. [13] read the irtr flag in icsr. if the irtr flag value is 0, the wait state is cancelled by clearing the iric flag as described in step [14] below. if the irtr flag value is 1 and the receive operation has finished, perform the issue stop condition processing described in step [15] below. [14] if the irtr flag value is 0, clear the iric fl ag to 0 to cancel the wait state. return to reading the iric flag, as described in step [12], to detect the end of the receive operation. [15] clear the wait bit in icmr to 0 to cancel the wait mode. then clear the iric flag to 0. the iric flag should be cleared when the value of wait is 0. (the stop condition may not be output properly when the issue stop condition instruction is executed if the wait bit was cleared to 0 after the iric flag is cleared to 0.) [16] read the final receive data in icdr. [17] write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. 1 9 a 2345 12345 678 9 data 1 data 1 master receive mode master transmit mode data 2 [3] [3] a [4] irtr = 1 [4] irtr = 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scl (master output) sda (slave output) sda (master output) iric irtr icdr user processing [1] trs cleared to 0 iric clearance [2] icdr read (dummy read) [6] iric clearance (cancel wait) [5] icdr read (data 1) [6] iric clearance figure 14.12 example of master receive mode operation timing (mls = ackb = 0, wait = 1)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 417 of 656 rej09b0071-0500 9 81345678 9 a a data 2 data 3 data 3 data 2 data 1 [3] [3] [8] [12] [12] stop condition generated [4] irtr = 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 1 clock cycle wait time bit 7 [4] irtr = 1 [13] irtr = 1 [13] irtr = 0 [15] wait cleared to 0 iric clearance [14] iric clearance [11] iric clearance [6] iric clearance user processing [10] icdr read (data 2) [16] icdr read (data 3) [ 9 ] trs set to 1 [7] ackb set to 1 scl (master output) sda (slave output) sda (master output) iric irtr icdr [17] stop condition issued 2 figure 14.13 example of master receive mode stop co ndition generation timing (mls = ackb = 0, wait = 1) 14.4.5 slave recei ve operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the slave device compares its own address with th e slave address in the first frame following the establishment of the start condition issued by the master device. if the addresses match, the slave device operates as the slave device designated by the master device. figure 14.14 is a flowchart showing an example of slave receive mode operation.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 418 of 656 rej09b0071-0500 start initialize set mst = 0 and trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no clear iric in iccr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no [1] [2] [3] [4] [5] [6] [7] [8] is next receive the last one? read icdr read iric in iccr iric = 1? clear iric in iccr set ackb = 0 in icsr read icdr read iric in iccr read icdr iric = 1? clear iric in iccr end general call address processing * description omitted slave transmit mode [1] select slave receive mode. [2] wait for the first byte to be received (slave address). [3] start receiving. the first read is a dummy read. [4] wait for the transfer to end. [5] set acknowledge data for the last receive. [6] start the last receive. [7] wait for the transfer to end. [8] read the last receive data. figure 14.14 flowchart for slave transmit mode (example)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 419 of 656 rej09b0071-0500 the reception procedure and operations in slave receive mode are described below. 1. set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. 2. when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. 3. when the slave address matches in the firs t frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/ w ) is 0, the trs bit in iccr remains clear ed to 0, and slave receive operation is performed. 4. at the 9th clock pulse of th e receive frame, the slave device drives sda low and returns an acknowledge signal. at the same time, the iric flag in i ccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation conti nues. if the rdrf internal flag has been set to 1, the slave device drives scl low from the fall of the receive clock until data is read into icdr. 5. read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. read the irdr flag and clear the iric flag to 0 consecu tively, with no interrupt processing occurring between them. if the time needed to transmit one byte of data elapses before the iric flag is cleared, it will not be possible to determine when the transfer has completed. receive operations can be performed continuously by repeating steps [4] and [5]. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 420 of 656 rej09b0071-0500 sda (master output) sda (slave output) 2 1 2 1 4 36 58 7 9 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition issuance scl (slave output) address + r/ w address + r/ w [5] icdr read [5] iric clearance user processing slave address data 1 [4] a r/ w figure 14.15 example of sl ave receive mode operation timing (1) (mls = ackb = 0)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 421 of 656 rej09b0071-0500 sda (master output) sda (slave output) 2 14 36 58 7 9 8 7 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) data 2 data 2 data 1 data 1 [5] icdr read [5] iric clearance user processing data 2 data 1 [4] [4] a a figure 14.16 example of sl ave receive mode operation timing (2) (mls = ackb = 0)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 422 of 656 rej09b0071-0500 14.4.6 slave transmit operation if the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (r/ w ) is 1 (read), the trs bit in iccr is automatically set to 1 and the mode changes to slave transmit mode. figure 14.17 shows the sample flowchart for the operations in slave transmit mode. end write transmit data in icdr clear iric in iccr clear iric in iccr clear acke to 0 in iccr (ackb = 0 clear) clear iric in iccr read iric in iccr read ackb in icsr set trs = 0 in iccr read icdr read iric in iccr iric = 1? yes yes no no iric = 1? yes no [1], [2] if the slave address matches to the address in the first frame following the start condition detection and the r/ w bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [8] set slave receive mode. [6] read iric in iccr [7] clear acknowledge bit data [ 9 ] dummy read (to release the scl line). [10] wait for stop condition [3], [5] set transmit data for the second and subsequent bytes. [3], [4] wait for 1 byte to be transmitted. [4] determine end of transfer. slave transmit mode end of transmission (ackb = 1)? clear iric in iccr figure 14.17 sample flowchart for slave transmit mode
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 423 of 656 rej09b0071-0500 in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signa l. the transmission procedure and operations in slave transmit mode are described below. 1. initialize slave receive mode and wait for slave address reception. when making initial settings for slave receive mode , set the acke bit in iccr to 1. this is necessary in order to enable reception of th e acknowledge bit after entering slave transmit mode. 2. when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th cloc k pulse and returns an acknowledge signal. if the 8th data bit (r/ w ) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the iric flag is set to 1 at the rise of the 9th clock. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. at the same time, the tdre internal flag is set to 1. the slave device drives scl low from the fall of the transmit clock until icdr data is written, to disable the master device to output the next transfer clock. 3. after clearing the iric flag to 0, write data to icdr. at this time, the tdre internal flag is cleared to 0. the written data is transferred to icdrs, and the tdre internal and iric flags are set to 1 again. the slave device sequentially sends the data written into icdrs in accordance with the clock output by the master device. the iric flag is cleared to 0 to detect the end of transmission. processing from the icdr writing to the iric flag clearing should be performed continuously. prevent any other interrupt processing from being inserted. if the time for transmission of one frame of data has passed before the iric clearing, the end of transmission cannot be determined. 4. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. this acknowledge signal is stored in the ackb bit in icsr if the acke bit in has been set to 1, so the ackb bit can be used to determine whether the transfer operation was performed successfully. when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. when the tdre internal flag is 0, the data written into icdr is transferred to icdrs, transmission starts, and the tdre internal and iric flags are set to 1 again. if the tdre in ternal flag has been set to 1, this slave device drives scl low from the fall of the transmit clock until data is written to icdr. 5. to continue transmission, write the next data to be transmitted into icdr. the tdre internal flag is cleared to 0. the iric flag is cleared to 0 to detect the end of transmission. processing from the icdr register writing to the iric flag clearing should be performed continuously. prevent any other interrupt processing from being inserted. transmit operations can be performed continuously by repeating steps [4] and [5]. 6. clear the iric flag to 0.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 424 of 656 rej09b0071-0500 7. to end transmission, clear the acke bit in iccr to 0, to clear the acknowledge bit stored in the ackb bit to 0. 8. clear the trs bit to 0 for the next ad dress reception, to set slave receive mode. 9. dummy-read icdr to release sda on the slave side. 10. when the stop condition is detected, that is, when sda is changed from low to high when scl is high, the bbsy flag in iccr is cleared to 0 and the stop flag in icsr is set to 1. at the same time, the iric flag is set to 1. if the iric flag has been set, it is cleared to 0. to restart slave transmit mode operation, make the initial settings once again. sda (master output) sda (slave output) 2 1 2 1 4 36 58 7 9 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 icdrt icdrs iric tdre scl (master output) scl (slave output) slave receive mode slave transmit mode [3] icdr write user processing data 1 data 1 data 2 data 1 data 2 data 2 a r/ w a [3] iric clearance [3] iric clearance [5] iric clearance [5] icdr write [2] [4] figure 14.18 example of slave transmit mode operation timing (mls = 0)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 425 of 656 rej09b0071-0500 14.4.7 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 14.19 shows the iric set timing and scl control. (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) scl sda iric user processing write to icdr (transmit) or read icdr (receive) clear iric clear iric clear iric 1 a 8 1 1 a 7 1 2 2 2 2 2 2 89 7 (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) scl sda iric user processing (c) when fs = 1 and fsx = 1 (synchronous serial format) write to icdr (transmit) or read icdr (receive) 8 89 8 7 1 8 7 1 figure 14.19 iric setting timing and scl control
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 426 of 656 rej09b0071-0500 14.4.8 operation using the dtc (h8s/2268 group only) the i 2 c bus format provides for selection of the slave device and transfer direction by means of the slave address and the r/ w bit, confirmation of reception w ith acknowledge bit, indication of the last frame, and so on. therefore, continuous da ta transfer using the dtc must be carried out in conjunction cpu processing by means of interrupts. table 14.5 shows some example of processing usi ng the dtc. these examples assume that the number of transfer data bytes is know in slave mode. table 14.5 flags and transfer states item master transmit mode master receive mode slave transmit mode slave receive mode slave address + r/w bit transmission/ reception transmission by dtc (icdr write) transmission by cpu (icdr write) reception by cpu (icdr read) reception by cpu (icdr read) dummy data read ? processing by cpu (icdr read) ? ? actual data transmission/re ception transmission by dtc (icdr write) reception by dtc (icdr read) transmission by dtc (icdr write) reception by dtc (icdr read) dummy data (h ff) write ? ? processing by dtc (icdr write) ? last frame processing not necessary reception by cpu (icdr read) not necessary reception by cpu (icdr read) transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: end condition issuance by cpu not necessary automatic clearing on detection of end condition during transmission of dummy data (h ff) not necessary setting of number of dtc transfer data frames transmission: actual data count + 1 (+ 1 equivalent to slave address + r/ w bits) reception: actual data count transmission: actual data count + 1 (+ 1 equivalent to dummy data (h ff)) reception: actual data count
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 427 of 656 rej09b0071-0500 14.4.9 noise canceler the logic levels at the scl and sda pins are routed through noise cancellors before being latched internally. figure 14.20 shows a block diagram of the noise cancelled circuit. the noise cancellor consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. system clock period sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 14.20 block diagram of noise cancellor 14.4.10 initialization of internal state the iic has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed by (1) setting bits clr3 to clr0 in the ddcswr register or (2) clearing the ice bit. for details of settings for bits clr3 to clr0, see section 14.3.8, ddc switch register (ddcswr). scope of initialization: the initialization executed by this function covers the following items: ? tdre and rdrf internal flags ? transmit/receive sequencer and internal operating clock counter ? internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.)
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 428 of 656 rej09b0071-0500 the following items are not initialized: ? actual register values (icdr, sar, sarx, icmr, iccr, icsr, ddcswr, and stcr) ? internal latches used to retain register read information for setting/clearing flags in the icmr, iccr, icsr, and ddcswr registers ? the value of the icmr register bit counter (bc2 to bc0) ? generated interrupt sources (interrupt sources transferred to the interrupt controller) notes on initialization: ? interrupt flags and interrupt sources are not cl eared, and so flag clearing measures must be taken as necessary. ? basically, other register flags are not cleared e ither, and so flag clearing measures must be taken as necessary. ? when initialization is performed by means of the ddcswr register, the write data for bits clr3 to clr0 is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. ? if a flag clearing setting is made during transmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. the value of the bbsy bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the scl and sda pins, the bbsy bit may be cleared as a result. similarly, state switching of other bits and flags may also have an effect. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state. 1. execute initialization of the internal state according to the setting of bits clr3 to clr0, or according to the ice bit. 2. execute a stop condition issuance instruction (write 0 to bbsy and scp) to clear the bbsy bit to 0, and wait for two transfer rate clock cycles. 3. re-execute initialization of the internal state according to the setting of bits clr3 to clr0, or according to the ice bit. 4. initialize (re-set) the iic registers.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 429 of 656 rej09b0071-0500 14.5 interrupt source iici is the interrupt source of iic. table 14.6 shows each interrupt sour ce and its priority. the iccr interrupt enable bit sets each interrupt and the setting is independently sent to the interrupt controller. table 14.6 iic interrupt source channel name enable bit interrupt source interrupt flag interrupt priority 0 iici0 ieic i 2 c bus interface interrupt request iric high 1 iici1 ieic i 2 c bus interface interrupt request iric low 14.6 usage notes 1. in master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the i 2 c bus, neither condition will be output correc tly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. note that scl may not yet have gone lo w when bbsy is cleared to 0. 2. either of the following two conditions will start the next transfer. pay attention to these conditions when reading or writing to icdr. ? write access to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) ? read access to icdr when ice = 1 and trs = 0 (including automatic transfer from icdrs to icdrr) 3. table 14.7 shows the timing of scl and sda output in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 430 of 656 rej09b0071-0500 table 14.7 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28 t cyc to 256 t cyc ns scl output high pulse width t sclho 0.5 t sclo ns scl output low pulse width t scllo 0.5 t sclo ns sda output bus free time t bufo 0.5 t sclo ? 1 t cyc ns start condition output hold time t staho 0.5 t sclo ? 1 t cyc ns retransmission start condition output setup time t staso 1 t sclo ns stop condition output setup time t stoso 0.5 t sclo + 2 t cyc ns data output setup time (master) t sdaso 1 t scllo ? 3 t cyc ns data output setup time (slave) 1 t scll ? 3 t cyc ns data output hold time t sdaho 3 t cyc ns 4. scl and sda inputs are sampled in synchronization with the internal clock. the ac timing therefore depends on the system clock cycle t cyc , as shown in table 25.8. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. 5. the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance a nd load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that th e scl rise time does not exceed th e values given in the table in table 14.8.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 431 of 656 rej09b0071-0500 table 14.8 permissible scl rise time (t sr ) values time indication iicx t cyc indication i 2 c bus specification (max.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 7.5 t cyc normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 1 17.5 t cyc normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 6. the i 2 c bus interface specifications for the scl an d sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t scyc and t cyc , as shown in table 14.7. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 14.9 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. t bufo fails to meet the i 2 c bus interface specifications at any fr equency. the solution is either (a) to provide coding to secure th e necessary interval (approximat ely 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst- case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjust ing the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 432 of 656 rej09b0071-0500 table 14.9 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz t sclho 0.5 t sclo (?t sr ) standard mode ?1000 4000 4000 4000 4000 4000 4000 high-speed mode ?300 600 950 950 950 950 950 t scllo 0.5 t sclo (?t sf ) standard mode ?250 4700 4750 4750 4750 4750 4750 high-speed mode ?250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 t bufo 0.5 t sclo ?1 t cyc standard mode ?1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 3950 * 1 ( ?t sr ) high-speed mode ?300 1300 750 * 1 825 * 1 850 * 1 888 * 1 900 * 1 t staho 0.5 t sclo ?1 t cyc standard mode ?250 4000 4550 4625 4650 4688 4700 (?t sf ) high-speed mode ?250 600 800 875 900 938 950 t staso 1 t sclo (?t sr ) standard mode ?1000 4700 9000 9000 9000 9000 9000 high-speed mode ?300 600 2200 2200 2200 2200 2200 t stoso 0.5 t sclo + 2 t cyc standard mode ?1000 4000 4400 4250 4200 4125 4100 (?t sr ) high-speed mode ?300 600 1350 1200 1150 1075 1050 t sdaso 1t scllo * 2 ?3t cyc standard mode ?1000 250 3100 3325 3400 3513 3550 (master) (?t sr ) high-speed mode ?300 100 400 625 700 813 850 t sdaso 1 t scll * 2 ? 3 t cyc * 2 standard mode ?1000 250 3100 3325 3400 3513 3550 (slave) (?t sr ) high-speed mode ?300 100 400 625 700 813 850 t sdaho 3 t cyc standard mode 0 0 600 375 300 188 150 high-speed mode 0 0 600 375 300 188 150 notes: 1. does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.).
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 433 of 656 rej09b0071-0500 7. note on icdr read at end of master reception to halt reception after completion of a receive op eration in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes the sda pin from low to high when the scl pin is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data will not be transferred to icdr, and so it will not be possible to read the second byte of data. if it is necessary to read the second byte of data, issu e the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive da ta, first confirm that the bbsy bit in iccr is cleared to 0, the stop condition has been generated, and the bus has been released, then read icdr with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generatio n of the stop condition, the clock may not be output correctly in subsequent master transmission. clearing of the mst bit after completion of master transmission/reception, or other modifications of iic control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 14.21 (after confirming that the bbsy bit has been cleared to 0 in the iccr register). sda scl internal clock bbsy bit master receive mode icdr reading prohibited bit 0 a 8 9 stop condition (a) start condition execution of stop condition issuance instruction (0 written to bbsy and scp) confirmation of stop condition generation (0 read from bbsy) start condition issuance figure 14.21 points for attention con cerning reading of ma ster receive data
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 434 of 656 rej09b0071-0500 8. notes on start condition issuance for retransmission depending on the timing combination with the start condition issuance and the subsequently writing data to icdr, it may not be possible to issue the retransmission and the data transmission after retransmission condition issuance. after start condition issuance is done and determ ined the start conditi on, write the transmit data to icdr, as shown below. figure 14.22 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to icdr, together with the corresponding flowchart.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 435 of 656 rej09b0071-0500 sda iric scl ack bit 7 data output [3] (restart) start condition instruction issuance [4] iric determination [5] icdr write (next transmit data) [2] detemination of scl = low [1] iric determination start condition (retransmission) iric = 1? yes clear iric in icsr read scl pin write transmit data to icdr write bbsy = 1, scp = 0 (icsr) [1] [1] wait for end of 1-byte transfer [2] determine whether scl is low [3] issue restart condition instruction for transmission [4] determine whether start condition is generated or not [5] set transmit data (slave address + r/ w ) [2] [3] [4] [5] yes yes no no iric = 1? yes scl = low? start condition issuance? no no other processing note: program so that processing from [3] to [5] is executed continuously. 9 figure 14.22 flowchart and timing of start condition instruction issuance for retransmission
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 436 of 656 rej09b0071-0500 9. notes on i 2 c bus interface stop condition instruction issuance if the rise time of the 9th scl clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives scl low to effect a wait, after rising of the 9th scl clock, issue the stop condition after reading scl and determining it to be low, as shown below. stop condition scl iric [1] determination of scl = low 9 th clock vih high period secured [2] stop condition instruction isuuance sda as waveform rise is late, scl is detected as low figure 14.23 timing of stop condition issuance 10. notes on iric flag clearance when using wait function if the scl rise time exceeds the de signated duration or if the slave device is of the type that keeps scl low and applies a wait state when the wait function is used in the master mode of the i 2 c bus interface, read scl and clear the iric flag after determining that scl has gone low, as shown below. clearing the iric flag to 0 when wait is set to 1 and scl is being held at high level can cause the sda value to change before scl goes low, resulting in a start condition or stop condition being generated erroneously. scl scl = high duration maintained [1] judgement that scl = low [2] iric clearance v ih sda iric scl = low detected figure 14.24 iric flag clearance in wait = 1 status
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 437 of 656 rej09b0071-0500 11. notes on icdr reads and iccr access in slave transmit mode in a transmit operation in the slave mode of the i 2 c bus interface, do not read the icdr register or read or write to the iccr register during the period indicated by the shaded portion in figure 14.25. normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem w ith reading the icdr register or reading or writing to the iccr register. to ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. (1) make sure that reading received data from the icdr register, or reading or writing to the iccr register, is completed before the ne xt slave address receive operation starts. (2) monitor the bc2 to bc0 counter in the icmr register and, when the value of bc2 to bc0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the icdr register, or reading or writing to the iccr register. sda r/w waveforms if problem occurs bit 7 icdr write data transmission period when icdr reads and iccr reads and writes are prohibited (6 system clock cycles) detection of 9th clock cycle rising edge a 89 scl trs address received figure 14.25 icdr read and iccr access timing in slave transmit mode
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 438 of 656 rej09b0071-0500 12. notes on trs bit setting in slave mode from the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next scl pin signal is detected (the period indicated as (a) in figure 14.26) in the slave mode of the i 2 c bus interface, the value set in the trs bit in the iccr register is effective immediately. however, at other times (indicated as (b) in figure 14.26) the value set in the trs bit is put on hold until the next rising edge of the 9th clock cycle or stop cond ition is detected, rather than taking effect immediately. this results in the actual internal value of the trs bit remaining 1 (transmit mode) and no acknowledge bit being sent at th e 9th clock cycle address receive completion in the case of an address receive operation following a rest art condition input with no stop condition intervening. when receiving an address in the slave mode , clear the trs bit to 0 during the period indicated as (a) in figure 14.26. to cancel the holding of the sc l bit low by the wait function in the slave mode, clear the trs bit to 0 and then perform a dummy read of the icdr register. (a) restart condition icdr dummy read detection of 9th clock cycle rising edge trs bit set detection of 9th clock cycle rising edge 89 (b) data transmission sda scl trs 123456789 a address reception trs bit setting hold time figure 14.26 trs bit setting timing in slave mode
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 439 of 656 rej09b0071-0500 13. notes on icdr reads in transmit mode and icdr writes in receive mode when attempting to read icdr in the transmit mode (trs = 1) or write to icdr in the receive mode (trs = 0) under certain conditions, th e scl pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the scl bus line before the icdr register access operation can take place properly. when accessing icdr, always change the setting to the transmit mode before performing a read operation, and always change the setting to the receive mode before performing a write operation. 14.notes on acke bit and trs bit in slave mode when using the i 2 c bus interface, if an address is recei ved in the slave mode immediately after 1 is received as an acknowledge bit (ackb = 1) in the transmit mode (trs = 1), an interrupt may be generated at the rising edge of the 9t h clock cycle if the address does not match. when performing slave mode operations using the i 2 c bus interface module, make sure to do the following. (1) when a 1 is received as an acknowledge bit for the final transmit data after completing a series of transmit operations, clear the acke bit in the iccr register to 0 to initialize the ackb bit to 0. (2) in the slave mode, change the setting to the receive mode (trs = 0) before the start condition is input. to ensure that the switch from the slave transmit mode to the slave receive mode is accomplished properly, end the transmission as described in figure 14.17. 15. notes on arbitration lost in master mode the i 2 c bus interface recognizes the data in tr ansmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. when arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is co mpared with the value set in the sar or sarx register as an address. if the receive data matches with the address in the sar or sarx register, the i 2 c bus interface erroneously recognizes th at the address call has occurred. (see figure 14.27.) in multi-master mode, a bus conflict could happen. when the i 2 c bus interface is operated in master mode, check the state of the al bit in the icsr register every time after one frame of data has been transmitted or received. when arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 440 of 656 rej09b0071-0500 sa sla r/ w sa sla r/ w a data2 sa sla r/ w a sla r/ w a data3 a data4 data1 i 2 c bus interface (master transmit mode) transmit data match transmit timing match ? receive address is ignored ? automatically transferred to slave receive mode ? receive data is recognized as an address ? when the receive data matches to the address set in the sar or sarx register, the i 2 c bus interface operates as a slave device. ? arbitration is lost ? the al flag in icsr is set to 1 transmit data does not match other device (master transmit mode) i 2 c bus interface (slave receive mode) data contention figure 14.27 diagram of erroneous operation when arbitration is lost though it is prohibited in the normal i 2 c protocol, the same problem may occur when the mst bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. in multi-master mode, pay attention to the setting of the mst bit when a bus conflict may occur. in this case, the mst bit in the iccr register s hould be set to 1 according to the order below. (1) make sure that the bbsy flag in the iccr register is 0 and the bus is free before setting the mst bit. (2) set the mst bit to 1. (3) to confirm that the bus was not entered to the busy state while the mst bit is being set, check that the bbsy flag in the iccr register is 0 immedi ately after the mst bit has been set. 16. notes on wait operation in master mode when attempting to use the wait function in master mode, if the interrupt flag iric bit is cleared from 1 to 0 between the falling edges of the seventh and eighth clock pulses, the lsi may fail to enter wait status after the falling edge of the eighth clock pulse and instead output the ninth clock pulse continuously. when using the wait function, keep the following points in mind with regard to clearing the iric flag. ensure that the iric flag is set to 1 at the rising edge of the ninth clock pulse and cleared to 0 before the rising edge of the seventh clock pulse (when the counter value in bc2 to bc0 is 2 or higher).
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 441 of 656 rej09b0071-0500 if clearing of the iric flag is delayed due to interrupt handling or the like and the bc counter value is 1 or 0, confirm that the scl pin signal is low level after the bc2 to bc0 counter value has reached 0 before clearing the iric flag. (see figure 14.28.) 9 a sda scl bc2 to bc0 iric (operation example) a send/receive data confirm scl = low level clear iric iric flag may be cleared iric flag may be cleared iric flag may not be cleared clear iric when bc2 to bc0 2 send/receive data 0765432 765 12345678 9 123 1 figure 14.28 timing of iric flag clearing during wait operation 17. interrupt during module stop mode when the module is stopped in the state that an interrupt is requested, the interrupt source of the cpu or activation source of the dtc * is not cleared. be sure to enter module stop mode by disabling the interrupt beforehand. note: * supported only by the h8s/2268 group. 18. assignment and selection of register addresses some i 2 c bus interface registers are assigned to the sa me address as other registers. register selection is performed by means of the iice bit in the serial control register x (scrx). for details on register addresses, see section 24, list of registers.
section 14 i 2 c bus interface (iic) (supported as an option by h8s/2264 group) rev. 5.00 sep. 01, 2009 page 442 of 656 rej09b0071-0500
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 443 of 656 rej09b0071-0500 section 15 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to ten analog input channels to be selected. a block diagram of the a/d converter is shown in figure 15.1. 15.1 features ? 10-bit resolution ? ten input channels ? conversion time: 6.3 s per channel (at 20.5 mhz operation) ? two operating modes single mode: single-channel a/d conversion scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers conversion results are held in a 16-bit data register for each channel. ? sample and hold function ? three methods conversion start software 16-bit timer pulse unit (tpu or tmr) conversion start trigger external trigger signal ? interrupt request an a/d conversion end interrupt request (adi) can be generated. ? module stop mode can be set ? selectable range of voltages of analog inputs the range of voltages of analog inputs to be converted can be specified using the vref signal as the analog reference voltage. adcms35b_000020020700
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 444 of 656 rej09b0071-0500 module data bus control circuit internal data bus bus interface 10-bit d/a converter comparator + sample-and- hold circuit adi interrupt signal adcr adcsr addrd addrc addrb multiplexer addra an0 an1 an2 an3 an4 an5 an6 an7 an8 an 9 legend: adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d adtrg conversion start trigger from tpu or 8-bit timer off while waiting for a/d conversion on during a/d conversion avcc vref av ss successive approximations register /2 /4 /8 /16 figure 15.1 block diagram of a/d converter
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 445 of 656 rej09b0071-0500 15.2 input/output pins table 15.1 summarizes the input pins used by the a/ d converter. the eight analog input pins are divided into two groups each of which consists of four channels; analog input pins 0 to 3 (an0 to an3) comprising group 0 and analog input pins 4 to 7 (an4 to an7) comprising group 1. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. the vref pin is the a/d conversion reference voltage pin. table 15.1 pin configuration pin name symbol i/o function analog power supply pin avcc input analog block power supply and reference voltage analog ground pin avss input analog block ground and reference voltage reference voltage pin vref input reference voltage for a/d conversion analog input pin 0 an0 * input analog input pin 1 an1 * input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input pins analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input pins analog input pin 8 an8 input analog input pin 9 an9 input analog input pins a/d external trigger input pin adtrg input external trigger input pin for starting a/d conversion note: * an0 and an1 can be used only when vcc = avcc.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 446 of 656 rej09b0071-0500 15.3 register descriptions the a/d converter has the following registers. for details on the module stop control register, refer to section 22.1.2, module stop control registers a to d (mstpcra to mstpcrd). ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) ? a/d control register (adcr) 15.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 15.2. the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converte r is 8 bits width. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. therefore, when reading the addr, read only the uppe r byte, or read in word unit. table 15.2 analog input channels and corresponding addr registers analog input channel ch3 = 0 ch3 = 1 group 0 (ch2 = 0) group 1 (ch2 = 1) ? (ch2 = 0) ? (ch2 = 1) a/d data register to be stored results of a/d conversion an0 an4 setting prohibited setting prohibited addra an1 an5 setting prohibited setting prohibited addrb an2 an6 setting prohibited an8 addrc an3 an7 setting prohibited an9 addrd
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 447 of 656 rej09b0071-0500 15.3.2 a/d control/status register (adcsr) adcsr controls a/d conversion operations. bit bit name initial value r/w description 7 adf 0 r/(w) * 1 a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends on all specified channels in scan mode [clearing conditions] ? when 0 is written after reading adf = 1 ? when the dtc * 2 is activated by an adi interrupt, and the disel bit in dtc is 0 with the transfer counter other than 0 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt (adi) request enabled when 1 is set 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters the wait state. setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to power-down mode in which the a/d converter is halted, shown in table 22.1. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( adtrg ).
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 448 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. only set the scan bit while conversion is stopped (adst = 0). 0: single mode 1: scan mode 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 0 to 3 select analog input channels. when scan = 0 when scan = 1 0000: an0 0000: an0 0001: an1 0001: an0 to an1 0010: an2 0010: an0 to an2 0011: an3 0011: an0 to an3 0100: an4 0100: an4 0101: an5 0101: an4 to an5 0110: an6 0110: an4 to an6 0111: an7 0111: an4 to an7 1000: setting prohibited 1000: setting prohibited 1001: setting prohibited 1001: setting prohibited 1010: setting prohibited 1010: setting prohibited 1011: setting prohibited 1011: setting prohibited 1100: setting prohibited 1100: setting prohibited 1101: setting prohibited 1101: setting prohibited 1110: an8 1110: setting prohibited 1111: an9 1111: setting prohibited notes: 1. only 0 can be written to bit 7, to clear this bit. 2. supported only by the h8s/2268 group.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 449 of 656 rej09b0071-0500 15.3.3 a/d control register (adcr) the adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 6 trgs1 trgs0 0 0 r/w r/w timer trigger select 0 and 1 enables the start of a/d conversion by a trigger signal. only set bits trgs0 and trgs1 while conversion is stopped (adst = 0). 00: a/d conversion start by software is enabled 01: a/d conversion start by tpu conversion start trigger is enabled 10: a/d conversion start by 8-bit timer conversion start trigger is enabled 11: a/d conversion start by external trigger pin ( adtrg ) is enabled 5, 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits specify the a/d conversion time. the conversion time should be changed only when adst = 0. specify a setting that gives a value within the range shown in table 26.9 or 26.22 in section 26, electrical characteristics. 00: conversion time = 530 states (max.) 01: conversion time = 266 states (max.) 10: conversion time = 134 states (max.) 11: conversion time = 68 states (max.) 1, 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 450 of 656 rej09b0071-0500 15.4 interface to bus master addra to addrd are 16-bit registers. as the data bus to the bus master is 8 bits wide, the bus master accesses to the upper byte of the registers di rectly while to the lowe r byte of the registers via the temporary register (temp). data in addr is read in the fo llowing way: when the upper-byte da ta is read, the upper-byte data will be transferred to the cpu and the lower-byte data will be transferred to temp. then, when the lower-byte data is read, the lower-byte data will be transferred to the cpu. when data in addr is read, the data should be read from the upper byte and lower byte in the order. when only the upper-byte data is read, the data is guaranteed. however, when only the lower-byte data is read, the data is not guaranteed. figure 15.2 shows data fl ow when accessing to addr. temp (h'40) addrnl (h'40) addrnh (h'aa) temp (h'40) addrnl (h'40) addrnh (h'aa) read the upper byte read the lower byte (n = a to d) (n = a to d) module data bus module data bus bus interface bus interface bus master (h'40) bus master (h'aa) figure 15.2 access to addr (when reading h'aa40)
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 451 of 656 rej09b0071-0500 15.5 operation the a/d converter operates by successive appr oximation with 10-bit resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit adst to 0 in adcsr. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 15.5.1 single mode in single mode, a/d conversion is to be performed only once on the specified single channel. the operations are as follows. 1. a/d conversion is started when the adst bit is set to 1, according to software, timer conversion start trigger, or external trigger input. 2. when a/d conversion is completed, the result is transferred to the corresponding a/d data register to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 452 of 656 rej09b0071-0500 adie adst adf state of channel 0 (an0) a/d conversion result 2 a/d conversion start a/d conversion result 1 addra addrb addrc addrd state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) note: * a/d conversion 1 set * set * set * clear * clear * idle idle idle idle a/d conversion 2 idle read conversion result * read conversion result * vertical arrows indicate instructions executed by software. figure 15.3 example of a/d converter operation (single mode, channel 1 selected)
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 453 of 656 rej09b0071-0500 15.5.2 scan mode in scan mode, a/d conversion is to be performed sequentially on the specified channels (four channels maximum). the operations are as follows. 1. when the adst bit is set to 1 by software, tpu, timer conversion start trigger, or external trigger, input, a/d conversion starts on the first channel in the group (an0 when ch3 and ch2 = 00, an4 when ch3 and ch2 = 01, or an8 when ch3 and ch2 = 10). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi in terrupt is requested after a/d conversion ends. conversion of the first channel in the group starts again. 4. steps [2] to [3] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and the a/d converter enters the wait state. adst adf addra addrb addrc addrd state of channel 0 (an0) notes: contimuous a/d conversion * 2 state of channel 1 (an1) state of channel 3 (an3) state of channel 2 (an2) clear * 1 clear * 1 set * 1 idle idle idle idle idle idle idle idle idle a/d conversion time a/d conversion 1 a/d conversion 2 a/d conversion 4 a/d conversion 3 a/d conversion 5 a/d conversion result 1 a/d conversion result 2 a/d conversion result 2 a/d conversion result 3 1. vertical arrows indicate instructions executed by software. 2. data currently being converted is ignored. figure 15.4 example of a/d converter operation (scan mode, channels an0 to an2 selected)
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 454 of 656 rej09b0071-0500 15.5.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 15.5 shows the a/d conversion timing. table 15.3 shows the a/d conversion time. as indicated in figure 15.5, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 15.3. specify the conversion time by setting bits cks0 and cks1 in adcr with adst cleared to 0. note that the specified conversion time should be longer than the value described in a/d conversion characteristics in section 25, electrical characteristics. in scan mode, the values given in table 15.3 apply to the first conversion time. the values given in table 15.4 apply to the second and subsequent conversions. (1) (2) t d t spl t conv address write signal input sampling timing adf legend: (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 15.5 a/d conversion timing
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 455 of 656 rej09b0071-0500 table 15.3 a/d conversion time (single mode) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay t d 18 ? 33 10 ? 17 6 ? 9 4 ? 5 input sampling time t spl ? 127 ? ? 63 ? ? 31 ? ? 15 ? a/d conversion time t conv 515 ? 530 259 ? 266 131 ? 134 67 ? 68 note: * all values represent the number of states. table 15.4 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 512 (fixed) 0 1 256 (fixed) 1 0 128 (fixed) 1 64 (fixed)
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 456 of 656 rej09b0071-0500 15.5.4 external trigger input timing a/d conversion can be externally triggered. when the trgs0 and trgs1 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 15.6 shows the timing. adtrg internal trigger signal adst a/d conversion figure 15.6 external trigger input timing 15.6 interrupt source the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. setting the adie bit to 1 enables adi interrupt requests while the bit adf in adcsr is set to 1 after a/d conversion is completed. in the h8s/2268 group, the dtc * can be activated by an adi interrupt. having the converted data read by the dtc * in response to an adi interrupt enables continuous conversion without imposing a load on software. table 15.5 a/d converter interrupt source name interrupt source interrupt source flag dtc activation * adi a/d conversion completed adf possible note: * supported only by the h8s/2268 group.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 457 of 656 rej09b0071-0500 15.7 a/d conversion accu racy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 15.7). ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 15.8). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 15.8). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between zero voltage and full- scale voltage. does not include offset error, fu ll-scale error, or quantization error (see figure 15.8). ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 458 of 656 rej09b0071-0500 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 15.7 a/d conversion accuracy definitions (1) fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 15.8 a/d conversion accuracy definitions (2)
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 459 of 656 rej09b0071-0500 15.8 usage notes 15.8.1 module stop mode setting operation of the a/d converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the a/d convert er to be halted. register access is enabled by clearing module stop mode. for details, refer to section 22, power-down modes. 15.8.2 permissible sign al source impedance this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. howe ver, for a/d conversion in single mode with a large capacitance provided externa lly, the input load will essentia lly comprise only the internal input resistance of 10 k , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 15.9). when converting a high-speed analog signal, a low-impedance buffer should be inserted. 15.8.3 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). a/d converter equivalent circuit this lsi 20 pf c in = 15 pf 10 k low-pass filter c to 0.1 mf sensor output impedance to 5 k sensor input figure 15.9 example of analog input circuit
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 460 of 656 rej09b0071-0500 15.8.4 range of analog power supply and other pin settings if the conditions below are not met, the reliability of the device may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann avcc. ? relationship between avcc, avss and vcc, vss set avss = vss as the relationship between avcc, avss and vcc, vss. if the a/d converter is not used, the avcc and avss pins must not be left open. in addition, analog input pins an0 and an1 can be used only when vcc = avcc. ? vref range the reference voltage input from the vref pin should be set to avcc or less. 15.8.5 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. fa ilure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an9), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. 15.8.6 notes on noise countermeasures a protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (an0 to an9), between avcc and avss, as shown in figure 15.10. also, the bypass capacitors connected to avcc and the filter capacitor connected to an0 to an9 must be connected to avss. if a filter capacitor is connected, the input currents at the analog input pins (an0 to an9) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the curr ent input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding circuit constants.
section 15 a/d converter rev. 5.00 sep. 01, 2009 page 461 of 656 rej09b0071-0500 avcc * 1 an0 to an 9 avss r in * 2 100 0.1 f 0.01 f 10 f notes: values are reference values. 1. 2. r in : input impedance vref * 1 figure 15.10 example of analog input protection circuit table 15.6 analog pin specifications item min. max. unit analog input capacitance ? 20 pf permissible signal source impedance ? 5 k 20 pf an0 to an 9 note: values are reference values. 10 k to a/d converter figure 15.11 analog input pin equivalent circuit
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section 16 d/a converter rev. 5.00 sep. 01, 2009 page 463 of 656 rej09b0071-0500 section 16 d/a converter the h8s/2268 group includes a d/a converter, while the h8s/2264 group does not. 16.1 features ? 8-bit resolution ? two output channels ? conversion time: 10 s, maximum (when load capacitance is 20 pf) ? output voltage: 0 v to vref ? module stop mode can be set module data bus bus interface internal data bus vref avcc da1 da0 avss 8-bit d/a control circuit legend: dacr: d/a control register dadr0: d/a data register 0 dadr1: d/a data register 1 dadr0 dadr1 dacr figure 16.1 block diagram of d/a converter dac0004b_000020020700
section 16 d/a converter rev. 5.00 sep. 01, 2009 page 464 of 656 rej09b0071-0500 16.2 input/output pins table 16.1 shows the pin configuration for the d/a converter. table 16.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground and reference voltage analog output pin 0 da0 output channel 0 analog output pin analog output pin 1 da1 output channel 1 analog output pin reference voltage pin vref input reference voltage for analog block 16.3 register description the d/a converter has the following registers. for details on the module stop control register, refer to section 22.1.2, module stop control registers a to d (mstpcra to mstpcrd). ? d/a data register 0 (dadr0) ? d/a data register 1 (dadr1) ? d/a control register (dacr) 16.3.1 d/a data registers 0 and 1 (dadr0 and dadr1) dadr0 and dadr1 are 8-bit readable/writable registers that store data for d/a conversion. when analog output is permitted, d/a data regist er contents are converted and output to analog output pins.
section 16 d/a converter rev. 5.00 sep. 01, 2009 page 465 of 656 rej09b0071-0500 16.3.2 d/a control register (dacr) dacr controls d/a converter operation. bit bit name initial value r/w description 7 daoe1 0 r/w d/a output enable 1 controls d/a conversion and analog output 0: analog output da1 is disabled 1: d/a conversion for channel 1 and analog output da1 are enabled 6 daoe0 0 r/w d/a output enable 0 controls d/a conversion and analog output 0: analog output da0 is disabled 1: d/a conversion for channel 0 and analog output da0 are enabled 5 dae 0 r/w d/a enable controls d/a conversion in conjunction with the daoe0 and daoe1 bits. when the dae bit is cleared to 0, d/a conversion for channels 0 and 1 are controlled individually. when dae is set to 1, d/a conversion for channels 0 and 1 are controlled as one. conversion result output is controlled by the daoe0 and daoe1 bits. for details, see table 16.2. 4 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified.
section 16 d/a converter rev. 5.00 sep. 01, 2009 page 466 of 656 rej09b0071-0500 table 16.2 d/a conversion control bit 5 bit 7 bit 6 dae daoe1 daoe0 description 0 0 0 disables d/a conversion 1 enables d/a conversion for channel 0 1 0 enables d/a conversion for channel 1 1 enables d/a conversion for channels 0 and 1 1 0 0 disables d/a conversion 1 enables d/a conversion for channels 0 and 1 1 0 1 16.4 operation two channels of the d/a converter can perform conversion individually. when the daoe bit in dacr is set to 1, d/a conve rsion is enabled and the conversion results are output. an example of d/a conversion of channel 0 is shown below. the operation timing is shown in figure 16.2. 1. write conversion data to dadr0. 2. when the daoe0 bit in dacr is set to 1, d/a conversion starts. after the interval of t dconv , the conversion results are output from the analog output pin da0. the conversion results are output continuously until dadr0 is modified or daoe0 bit is cleared to 0. the output value is calculated by the following formula: (dadr contents)/256 vref 3. conversion starts immedi ately after dadr0 is modified . after the interval of t dconv , conversion results are output. 4. when the daoe bit is cleared to 0, analog output is disabled.
section 16 d/a converter rev. 5.00 sep. 01, 2009 page 467 of 656 rej09b0071-0500 dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle adres dadr0 daoe0 da 0 conversion data (1) conversion data (2) high impedance state conversion result (1) conversion result (2) t dconv t dconv legend: t dconv : d/a conversion time figure 16.2 d/a conv erter operation example 16.5 usage notes 16.5.1 analog power supply current in power-down mode if this lsi enters a power-down mode such as software standby, watch, sub-active, sub-sleep, and module stop modes while d/a conversion is enabled, the d/a cannot retain analog outputs within the given d/a absolute accuracy although it retains digital values. the analog power supply current is approximately the same as that during d/a conversion. to reduce analog power supply current in power-down mode, clear the daoe0, daoe1 and dae bits to 0 to disable d/a outputs before entering the mode. 16.5.2 setting for module stop mode it is possible to enable/disable the d/a converter operation using the module stop control register, the d/a converter does not operate by the initial valu e of the register. the register can be accessed by releasing the module stop mode. for more details, see section 22, power-down modes.
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section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 469 of 656 rej09b0071-0500 section 17 lcd controller/driver the h8s/2268 has an on-chip segment type lcd control circuit, lcd driver, and power supply circuit, enabling it to directly drive an lcd panel. 17.1 features features of the lcd controller/driver are given below. ? display capacity duty cycle internal driver static 40 seg 1/2 40 seg 1/3 40 seg 1/4 40 seg ? lcd ram capacity 8 bits 20 bytes (160 bits) byte or word access to lcd ram ? the segment output pins can be used as ports. h8s/2268 group: seg40 to seg1 pins can be used as ports in groups of eight. h8s/2264 group: seg24 to seg1 pins can be used as ports in groups of eight. ? common output pins not used because of th e duty cycle can be used for common double- buffering (parallel connection). with 1/2 duty, parallel connection of com1 to com2, and of com3 to com4, can be used in static mode, parallel connection of com1 to com2, com3, and com4 can be used ? choice of 11 frame frequencies ? a or b waveform selectable by software ? built-in power supply split-resistance ? display possible in operating modes other than standby mode and module stop mode ? display possible during low-voltage operation by built-in triple step-up voltage circuit (supposrted only by the h8s/2268 group) ? module stop mode as the initial setting, lcd operation is halted. access to registers and lcd ram is enabled by clearing module stop mode. lcdsg00b_000020030700
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 470 of 656 rej09b0071-0500 figure 17.1 shows a block diagram of the lcd controller/driver. /16 to /2048 * 2 sub to sub/4 cl2 cl1 segn, do lpcr lcr lcr2 display timing generator lcd ram 20 bytes internal data bus 40-bit shift register lcd drive power supply (built-in step-up voltage circuit * 1 ) segment driver common data latch common driver m v1 v2 v3 v ss com1 com4 seg40 seg3 9 seg38 seg37 seg36 seg1 legend: lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 notes: 1. supported only by the h8s/2268 group. 2. the clock oscillator stops operating in subactive, subsleep, and watch mode. therefore, be sure to select a frequency between sub and sub/4. v cc figure 17.1 block diagram of lcd controller/driver
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 471 of 656 rej09b0071-0500 17.2 input/output pins table 17.1 shows the lcd controller/driver pin configuration. table 17.1 pin configuration name abbreviation i/o function segment output pins seg40 to seg1 output lcd segment drive pins (h8s/2268 group) all pins are multiplexed as port pins (setting programmable) (h8s/2264 group) seg24 to seg1 pins are multiplexed as port pins (setting programmable) common output pins com4 to com1 output lcd common drive pins pins can be used in parallel with static or 1/2 duty lcd power supply pins v1, v2, v3 ? used when a bypass capacitor is connected externally, and when an external power supply circuit is used v3 pin is lcd input reference power supply when triple step-up voltage circuit is used * . capacitance pins for lcd step-up voltage * c1, c2 ? capacitance pins for step-up voltage lcd drive power supply note: * supported only by the h8s/2268 group.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 472 of 656 rej09b0071-0500 17.3 register descriptions the lcd controller/driver has the following registers. ? lcd port control register (lpcr) ? lcd control register (lcr) ? lcd control register 2 (lcr2) ? lcdram 17.3.1 lcd port control register (lpcr) lpcr selects the duty cycle, lcd driver, and pin functions. bit bit name initial value r/w description 7 6 5 dts1 dts0 cmx 0 0 0 r/w r/w r/w duty cycle select 1 and 0 common function select the combination of dts1 and dts0 selects static, 1/2, 1/3, or 1/4 duty. cmx specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. 4 ? 0 ? reserved this bit is always read as 0 and should only be written with 0. 3 2 1 0 sgs3 sgs2 sgs1 sgs0 0 0 0 0 r/w r/w r/w r/w segment driver select 3 to 0 bits 3 to 0 select the segment drivers to be used. for details, see tables 17.3 and 17.4.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 473 of 656 rej09b0071-0500 table 17.2 duty cycle and common function selection bit 7: dts1 bit 6: dts0 bit 5: cmx duty cycle common drivers notes 0 0 0 static com1 com4, com3, and com2 can be used as ports (initial value) 1 com4 to com1 com4, com3, and com2 output the same waveform as com1 1 0 1/2 duty com2 to com1 com4 and com3 can be used as ports 1 com4 to com1 com4 outputs the same waveform as com3, and com2 outputs the same waveform as com1 1 0 0 1/3 duty com3 to com1 com4 can be used as a port * 1 com4 to com1 do not use com4 1 x 1/4 duty com4 to com1 ? legend: x: don?t care notes: com4 to com1 function as ports when the setting of sgs3 to sgs0 is 0000. * cannot be used as a port when the sups bit in lcr2 is 1 in the h8s/2268 group. set the sups bit to 0 when using as a port.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 474 of 656 rej09b0071-0500 table 17.3 segment driver selection (1) (h8s/2268 group) function of pins seg40 to seg1 bit 3: sgs3 bit 2: sgs2 bit 1: sgs1 bit 0: sgs0 seg40 to seg33 seg32 to seg25 seg24 to seg17 seg16 to seg9 seg8 to seg1 0 0 0 0 port port port port port 1 seg port port port port 1 0 seg seg port port port 1 seg seg seg port port 1 0 0 seg seg seg seg port 1 seg seg seg seg seg 1 x setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited 1 x x x setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited legend: x: don?t care note: com4 to com1 also function as ports when the setting of sgs3 to sgs0 is 0000.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 475 of 656 rej09b0071-0500 table 17.4 segment driver selection (2) (h8s/2264 group) function of pins seg40 to seg1 bit 3: sgs3 bit 2: sgs2 bit 1: sgs1 bit 0: sgs0 seg40 to seg25 seg24 to seg17 seg16 to seg9 seg8 to seg1 0 0 0 0 ? port port port 1 setting prohibited setting prohibited setting prohibited setting prohibited 1 0 seg port port port 1 seg seg port port 1 0 0 seg seg seg port 1 seg seg seg seg 1 x setting prohibited setting prohibited setting prohibited setting prohibited 1 x x x setting prohibited setting prohibited setting prohibited setting prohibited legend: x: don?t care note: com4 to com1 also function as ports when the setting of sgs3 to sgs0 is 0000.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 476 of 656 rej09b0071-0500 17.3.2 lcd control register (lcr) lcr performs lcd power supply split-resistance conn ection control and display data control, and selects the frame frequency. bit bit name initial value r/w description 7 ? 1 r/w lcd disable bit this bit is always read as 1. the write value should always be 0. 6 psw 0 r/w lcd power supply split-resistance connection control bit 6 can be used to disconnect the lcd power supply split-resistance from v cc when lcd display is not required in a power-down mode, or when an external power supply is used. when the act bit is cleared to 0, and also in standby mode, the lcd power supply split- resistance is disconnected from v cc regardless of the setting of this bit. 0: lcd power supply split-resistance is disconnected from v cc 1: lcd power supply split-resistance is connected to v cc 5 act 0 r/w display function activate bit 5 specifies whether or not the lcd controller/driver is used. clearing this bit to 0 halts operation of the lcd controller/driver. the lcd drive power supply ladder resistance is also turned off, regardless of the setting of the psw bit. however, register contents are retained. 0: lcd controller/driver operation halted 1: lcd controller/driver operation enabled 4 disp 0 r/w display data control bit 4 specifies whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. 0: blank data is displayed 1: lcd ram data is displayed
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 477 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w frame frequency select 3 to 0 bits 3 to 0 select the operating clock and the frame frequency. in subactive mode, watch mode, and subsleep mode, the system clock ( ) is halted, and therefore display operations are not performed if one of the clocks from /16 to /2048 is selected. if lcd display is required in these modes, sub , sub /2, or sub /4 must be selected as the operating clock. for details, see table 17.5. note: 0 should be written to bit 7 after the other bits have been set. table 17.5 frame frequency selection frame frequency * 1 bit 3: cks3 bit 2: cks2 bit 1: cks1 bit 0: cks0 operating clock = 20 mhz = 2 mhz 0 x 0 0 sub 128 hz * 2 128 hz * 2 1 sub /2 64 hz * 2 64 hz * 2 1 x sub /4 32 hz * 2 32 hz * 2 1 0 0 0 /16 ? 488 hz 1 /32 ? 244 hz 1 0 /64 ? 122 hz 1 /128 610 hz 61 hz 1 0 0 /256 305 hz 30.5 hz 1 /512 152.6 hz ? 1 0 /1024 76.3 hz ? 1 /2048 38.1 hz ? legend: x: don?t care notes: 1. when 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 2. this is the frame frequency when sub = 32.768 khz.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 478 of 656 rej09b0071-0500 17.3.3 lcd control register 2 (lcr2) lcr2 controls switching between the a waveform and b waveform, selects clock for step-up voltage circuit, selects power supply, and selects the duty ratio for charge/discharge pulse that controls to separate power supply divider resistance from power supply circuit. bit bit name initial value r/w description 7 lcdab 0 r/w a waveform/b waveform switching control bit 7 specifies whether the a waveform or b waveform is used as the lcd drive waveform. 0: drive using a waveform 1: drive using b waveform 6 ? 1 ? reserved these bits are always read as 1 and cannot be modified. 5 hcks 0 r/w (h8s/2268 group) triple step-up voltage circuit clock select this bit selects a clock used for triple step-up voltage circuit. this bit selects a clock which divides a clock specified by the lcd operating control register (lcr) by 4 or 8 as step-up voltage circuit clock. 0: a clock, which divides a lcd operating clock by 4, is selected as step-up voltage circuit clock 1: a clock, which divides a lcd operating clock by 8, is selected as step-up voltage circuit clock (h8s/2264 group) reserved 0 should be written to this bit.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 479 of 656 rej09b0071-0500 bit bit name initial value r/w description 4 sups 0 r/w (h8s/2268 group) drive power select triple step-up voltage circuit control the triple step-up voltage circuit stops operation when vcc is selected as drive power. the triple step-up voltage circuit starts operation when lcd input reference voltage (v lcd3 ) is selected as drive power. 0: drive power is vcc, triple step-up voltage circuit halts 1: drive power is triple step-up voltage of the lcd input reference voltage (v lcd3 ), triple step-up voltage circuit operates (h8s/2264 group) reserved 0 should be written to this bit. 3 2 1 0 cds3 cds2 cds1 cds0 0 0 0 0 r/w r/w r/w r/w selection of duty ratio for charge/discharge pulse duty ratio is selected during the power supply divider resistance is connected to power supply circuit. when the duty ratio of 0 is selected, the power supply divider resistance is fixed to the state that the resistance is separated from the power supply circuit. therefore, supply the power to pins v 1 , v 2 , and v 3 from the external circuit. the charge/discharge pulses have the waveform shown in figure 17.2. the duty ratio is represented by t c /t w . 0000: duty ratio = 1 (stack at high) 0001: duty ratio = 1/8 0010: duty ratio = 2/8 0011: duty ratio = 3/8 0100: duty ratio = 4/8 0101: duty ratio = 5/8 0110: duty ratio = 6/8 0111: duty ratio = 0 (stack at low) 10xx: duty ratio = 1/16 11xx: duty ratio = 1/32 legend: x: don?t care
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 480 of 656 rej09b0071-0500 figure 17.2 shows the waveform of the charge/discharge pulses. the duty cycle is tc/tw. com1 charge/discharge pulses tc tdc tw 1 frame legend: tc: power supply split-resistance connected tdc: power supply split-resistance disconnected figure 17.2 a waveform 1/2 duty 1/2 vias
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 481 of 656 rej09b0071-0500 the relationships between the lcd operating clock and step-up voltage clock, and between bits cks3 to cks0 in lcd control register (lcr) and bit hcks in lcd control register 2 (lcr2) are shown below. lcr bit 3 bit 2 bit 1 bit 0 frame frequency step-up voltage circuit clock frequency * cks3 cks2 cks1 cks0 lcr2 bit 5 hcks * lcd clock step-up voltage circuit clock * = 20 mhz = 2 mhz = 20 mhz = 2 mhz 0 sub /4 8192 hz 0 x 0 0 1 sub 128 hz 0 sub /8 4096 hz 0 x 0 1 1 sub /2 64 hz 0 sub /16 2048 hz 0 x 1 x 1 sub /4 sub /32 32 hz 1024 hz 0 64 ? 31.3 khz 1 0 0 0 1 /16 ? 488 hz 0 128 ? 15.6 khz 1 0 0 1 1 /32 ? 244 hz 0 256 ? 7.81 khz 1 0 1 0 1 /64 ? 122 hz ? 0 512 39.1 khz 3.91 khz 1 0 1 1 1 /128 610 hz 61 hz 0 1024 19.5 khz 1.95 khz 1 1 0 0 1 /256 305 hz 30.5 hz 977 khz 0 2048 9.77 khz ? 1 1 0 1 1 /512 152.6 hz ? 0 4096 4.88 khz ? 1 1 1 0 1 /1024 76.3 hz ? 1 1 1 1 0 /2048 8192 38.1 hz ? 2.44 khz ? 1 16384 1.22 khz ? legend: x: don?t care note: * supported only by the h8s/2268 group.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 482 of 656 rej09b0071-0500 17.4 operation 17.4.1 settings up to lcd display to perform lcd display, the hardware and softwa re related items described below must first be determined. 1. hardware settings a. using 1/2 duty when 1/2 duty is used, interconnect pins v 2 and v 3 as shown in figure 17.3. v1 v2 v3 v cc v ss figure 17.3 handling of lcd drive power supply when using 1/2 duty b. large-panel display as the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. if the display lacks sharpness when using a large panel, refer to section 17.4.6, boosting the lcd drive power supply. when static or 1/2 duty is selected, the common output drive capability can be increased. set cmx to 1 when selecting the duty cycle. in this mode, with a static duty cycle pins com4 to com1 output the same waveform, and with 1/2 duty the com1 waveform is output from pins com2 and com1, and the com2 waveform is output from pins com4 and com3. c. lcd drive power supply setting with the h8s/2268 and 2264, there are two ways of providing lcd power: by using the on-chip power supply circuit, or by using an external power supply circuit. when an external power supply circuit is used for the lcd drive power supply, connect the external power supply to the v1 pin.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 483 of 656 rej09b0071-0500 2. software settings a. duty selection any of four duty cycles ? static, 1/2 duty, 1/3 duty, or 1/4 duty ? can be selected with bits dts1 and dts0. b. segment selection the segment drivers to be used can be selected with bits sgs3 to sgs0. 3. frame frequency selection the frame frequency can be selected by setti ng bits cks3 to cks0. the frame frequency should be selected in accordance with the lcd panel specification. for the clock selection method in watch mode, subactive mode, and subsleep mode, see section 17.4.4, operation in power-down modes. a. a or b waveform selection either the a or b waveform can be selected as the lcd waveform to be used by means of lcdab. b. lcd drive power supply selection when an external power supply circuit is used , turn the lcd drive power supply off with the psw bit. 17.4.2 relationship between lcd ram and display the relationship between the lcd ram and the di splay segments differs according to the duty cycle. lcd ram maps for the different duty cycles are shown in figures 17.4 to 17.7. after setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary ram, and display is started automatically when turned on. word- or byte-access instructions can be used for ram setting.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 484 of 656 rej09b0071-0500 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg40 h'fc53 h'fc40 seg40 seg40 seg40 seg3 9 seg3 9 seg3 9 seg3 9 seg2 seg2 seg2 seg2 seg1 seg1 seg1 seg1 com4 com3 com2 com1 com4 com3 com2 com1 figure 17.4 lcd ram map (1/4 duty) h'fc53 h'fc40 seg40 seg40 seg40 seg3 9 seg3 9 seg3 9 seg2 seg2 seg2 seg1 seg1 seg1 com3 space not used for display com2 com1 com3 com2 com1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 17.5 lcd ram map (1/3 duty)
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 485 of 656 rej09b0071-0500 h'fc53 h'fc40 h'fc4 9 seg40 seg40 seg3 9 seg3 9 seg38 seg38 seg37 seg37 seg4 seg4 seg3 seg3 seg2 seg2 seg1 seg1 display space space not used for display com2 com1 com2 com1 com2 com1 com2 com1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 17.6 lcd ram map (1/2 duty) h'fc53 h'fc40 h'fc44 seg40 seg3 9 seg38 seg37 seg36 seg35 seg34 seg33 display space space not used for display seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com1 com1 com1 com1 com1 com1 com1 com1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 17.7 lcd ram map (static mode)
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 486 of 656 rej09b0071-0500 m data (a) waveform with 1/4 duty (c) waveform with 1/2 duty (d) waveform with static output (b) waveform with 1/3 duty com1 com2 com3 com4 segn m data com1 com2 segn m data com1 segn m data 1 frame 1 frame 1 frame 1 frame com1 v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2,v3 vss v1 vss v1 vss v1 v2,v3 vss v1 v2,v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v1 v2 v3 vss v2 v3 vss com2 com3 segn figure 17.8 output waveforms fo r each duty cycl e (a waveform)
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 487 of 656 rej09b0071-0500 m data (a) waveform with 1/4 duty (c) waveform with 1/2 duty (d) waveform with static output (b) waveform with 1/3 duty com1 com2 com3 com4 segn m data com1 com2 segn m data com1 segn m data 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame com1 v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2,v3 vss v1 vss v1 vss v1 v2,v3 vss v1 v2,v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v1 v2 v3 vss v2 v3 vss com2 com3 segn figure 17.9 output waveforms fo r each duty cycle (b waveform)
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 488 of 656 rej09b0071-0500 table 17.6 output levels data 0 0 1 1 m 0 1 0 1 static common output v1 v ss v1 v ss segment output v1 v ss v ss v1 1/2 duty common output v2, v3 v2, v3 v1 v ss segment output v1 v ss v ss v1 1/3 duty common output v3 v2 v1 v ss segment output v2 v3 v ss v1 1/4 duty common output v3 v2 v1 v ss segment output v2 v3 v ss v1 17.4.3 triple step-up voltage circuit (supported only by the h8s/2268 group) the h8s/2268 group incorporates a triple step-up voltage circuit. triple voltage of liquid crystal input reference voltage (v lcd3 ) input from v3 pin can be used for the lcd driver. before enabling the step-up voltage circuit, duty cycle (1/3 duty or 1/4 duty), lcd driver or i/o pin function, and display data and frame frequency should be selected. around 0.1-f capacitor should be connected between c1 and c2, and voltage specified in section 25.2.6, lcd characteristics should be applied to v3 pin. after above settings, by selecting the step-up vo ltage circuit clock in lcd control register 2 (lcr2) and setting sups to 1, the triple step-up voltage circuit operates, voltage double of v lcd3 is generated for v2 pin, and voltage triple of v lcd3 is generated for v1pin. notes: 1. the triple step-up voltage circuit should only be used as lcd drive power of the h8s/2268 group. to drive large panel, power supply capacitance may be insufficient. in this case, vcc should be used as power supply or external power supply circuit should be used. 2. when the triple step-up voltage circuit is used, do not specify static or 1/2 duty as duty cycle. 3. do not use capacitance with polarity such as electrolytic capacito r as capacitance to be connected between c1 and c2.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 489 of 656 rej09b0071-0500 c1 c c c c note: c: 0.1 f (typ.) (0.05 to 0.2 f) c2 v1 v2 v3 figure 17.10 connection when trip le step-up voltage circuit used (supported only by the h8s/2268 group) 17.4.4 operation in power-down modes in the h8s/2268 and 2264, the lcd controller/driver can be operated even in the power-down modes. the operating state of the lcd controller/driver in the power-down modes is summarized in table 17.7. in subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless sub , sub /2, or sub /4 has been selected by bits cks3 to cks0, the clock will not be supplied and display will halt. since there is a possibility that a direct current will be applied to the lcd panel in this case, it is essential to ensure that sub , sub /2, or sub /4 is selected. in the software standby mode the segment output and common output pins switch to i/o port status. in this case if a port?s ddr or pcr bit is set to 1, a dc voltage could be applied to the lcd panel. therefore, ddr and pcr must never be set to 1 for ports being used for segment output or common output.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 490 of 656 rej09b0071-0500 table 17.7 power-down modes and display operation mode reset active sleep watch subactive subsleep software standby hardware standby module stop clock runs runs runs stops st ops stops stops stops stops * 4 w runs runs runs runs runs runs stops * 1 stops stops * 4 act = 0 stops stops stops stops stops stops stops * 2 stops * 2 stops display operation act = 1 stops functions functions functions * 3 functions * 3 functions * 3 stops * 2 stops * 2 stops notes: 1. the subclock oscillator does not stop, but clock supply is halted. 2. the lcd drive power supply is turned off regardless of the setting of the psw bit. 3. display operation is performed only if sub , sub /2, or sub /4 is selected as the operating clock. 4. the clock supplied to the lcd stops. 17.4.5 low-power lcd drive the simplest way to achieve low-power operation for an lcd power supply circuit is to use an internal division resistor. however, since the values of the internal resistors are fixed, a constant current continually flows from vcc to vss of the internal resistor. since the quantity of the current is independent of the dissipation current of an lcd panel, power is wasted in using a low-power lcd. this lsi incorporates a function that eliminates wastage of power. by using this function, a power supply circuit that is most suitable for the power of a given lcd panel can be obtained. ? principle ? as shown in figure 17.11, external capacitors are connected to v1, v2, and v3 of the lcd power supply terminals. ? the capacitors connected to v1 , v2, and v3 are repeatedly charged and discharged to retain required voltage levels in the cycles shown in figure 17.11. ? in this case, the charged voltages are equivalent to v1, v2, and v3, respectively. (in 1/3 bias operation, for example, the v2 voltage is two thirds of the v1 voltage and the v3 voltage is one third of the v1 voltage.) ? power is supplied to the lcd panel by the el ectric charges that ar e accumulated in these capacitors. ? the capacitances of the capacito rs and the charge-discharge period are determined by the quantity of power which the lcd panel requires. ? the charge-discharge period can be determined by software.
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 491 of 656 rej09b0071-0500 ? example of operation (1/3 bias operation) ? during charging period tc in figure 17.11, the voltages that are divided by the internal division resistors are applied to the v1, v2, and v3 terminals (the v2 voltage is two thirds of the v1 voltage and the v3 voltage is one third of the v1 voltage), and these voltages charge external capacitors c1, c2, and c3. even during this period, the lcd panel is being driven. ? in the subsequent discharge period tdc, the charge operation stops. the lcd panel is now driven by discharge of the charges accu mulated in the respective capacitors. ? at this point in time, the respective voltages fall slightly as the capacitors are discharged. attention must be paid so that the operation of the lcd panel is not affected, by selecting the proper charging period and the capacitance of the capacitors. ? the capacitors connected to th e v1, v2, and v3 terminals are repeatedly charged and discharged in the cycles shown in figure 17.11 and retain required voltages, keeping the lcd panel in operation. ? the capacitance of the capacitors and a char ge-discharge period is determined by the quantity of power in which the lcd panel requires. in addition, the charge-discharge period can be selected by cds3 to 0. ? in actuality, the capacitance of the capacitors and the charge-discharge period must be determined through experiment, on the basis of the power dissipation specifications of the lcd panel. this method, however, permits the most proper current value to be selected, compared with a case in which a dc current continually flows in the internal resistors. v1 v2 v3 c3 c2 c1 v1 potential v2 potential v3 potential charging period tc discharging period tdc vd1 vd2 vd3 voltage drop associated with discharging due to lcd panel driving v1 2/3 v1 1/3 power supply voltage fluctuation in 1/3 bias system figure 17.11 example of low-pow er-consumption lcd drive operation
section 17 lcd controller/driver rev. 5.00 sep. 01, 2009 page 492 of 656 rej09b0071-0500 17.4.6 boosting the lcd drive power supply when a large panel is driven, the on-chip power supply capacity may be insufficient. in this case, the power supply impedance must be reduced. this can be done by connecting bypass capacitors of around 0.1 to 0.3 f to pins v1 to v3, as s hown in figure 17.12, or by adding a split-resistance externally. this lsi v cc v ss v1 v2 v3 vr r r r r = c = 0.1 to 0.3 f several k to several m figure 17.12 connection of external split-resistance
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 493 of 656 rej09b0071-0500 section 18 dtmf generation circuit the h8s/2268 group contains a dual-tone multi-frequency generation circuit to generate dtmf signals. it is not contained in the h8s/2264 group. the dtmf signal consists of two types of sine waveforms and is used to access a switch device. the function of the dtmf signal is shown in the frequency matrix in figure 18.1. the dtmf generation circuit produces the frequencies corresponding to the numbers and symbols in the figure. 12 3ar1 (6 9 7 hz) r2 (770 hz) r3 (852 hz) r4 ( 9 41 hz) c1 (1,20 9 hz) c2 (1,336 hz) c3 (1,477 hz) c4 (1,633 hz) 45 6b 78 9 c * 0#d figure 18.1 dtmf frequencies 18.1 features ? generating dtmf frequency sine waveform from the system clock ( ) the system clock (2.0 to 20.4 mhz, with 400-khz steps) is divided to produce a 400-khz clock signal. this clock signal is then supplied to the feedback loop, comprised of a variant program divider and sine waveform counter to generate a dtmf frequency sine waveform. ? producing low distortion, stable sine waveforms sine waveforms signals are output from the high-precision resistor rudder-type d/a converter. in addition, one cycle is divided into 32, resulting in low-distortion stable signal waveforms. ? synthesis or single waveform output selectable synthesized row and column output, row output, or column output are selectable. ? module stop mode can be set. figure 18.2 shows the block diagram for the dtmf generation circuit. dtmf000b_000020020700
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 494 of 656 rej09b0071-0500 clock counter (2.0 to 20.4 mhz, with 400-khz steps) 400 khz dtlr sine waveform counterd/a toned av cc variant program divider sine waveform counter d/a variant progam divider feed back feedback legend: dtlr: dtmf load register dtcr: dtmf control register internal data bus dtcr column row figure 18.2 dtmf generation circuit diagram 18.2 input/output pins table 18.1 shows the pin configuration of the dtmf generation circuit. table 18.1 pin configuration name abbreviation input/output function analog power supply pin avcc input power supply of analog section dtmf signal output toned output dtmf signal output pin
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 495 of 656 rej09b0071-0500 18.3 register descriptions the dtmf generation circuit contains the following resisters: ? dtmf control register (dtcr) ? dtmf load register (dtlr) 18.3.1 dtmf control register (dtcr) the dtcr controls the dtmf generation circuit operation, column and row outputs, and selects the output frequency. bit bit name initial value r/w description 7 dten 0 r/w this bit controls dtmf generation 0: halts the dtmf generation circuit. 1: operates dtmf generation circuit. 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 cloe 0 r/w this bit controls column section outputs 0: inhibits dtmf signal output on column section (hi- impedance) 1: enables dtmf signal output on column section. 4 rwoe 0 r/w this bit controls column section outputs 0: inhibits dtmf signal output on row section (hi- impedance) 1: enables dtmf signal output on row section. 3 2 clf1 clf0 0 0 r/w r/w dtmf signal output frequency on column section 1 and 0 selects column dtmf signal frequency from c1 to c4. 00: column dtmf signal output frequency: 1209 hz (c1) 01: column dtmf signal output frequency: 1336 hz (c2) 10: column dtmf signal output frequency: 1447 hz (c3) 11: column dtmf signal output frequency: 1633 hz (c4) 1 0 rwf1 rwf0 0 0 r/w r/w dtmf signal output frequency on row section: 1, 0 selects column dtmf signal frequency from r1 to r4. 00: row dtmf signal output frequency: 697 hz (r1) 01: row dtmf signal output frequency: 770 hz (r2) 10: row dtmf signal output frequency: 852 hz (r3) 11: row dtmf signal output frequency: 941 hz (r4)
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 496 of 656 rej09b0071-0500 18.3.2 dtmf load register (dtlr) the dtlr sets the system clock division ratio for the dtmf generation circuit. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 4 3 2 1 0 dtl5 dtl4 dtl3 dtl2 dtl1 dtl0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w main clock division ratio 5 to 0 these bits set the system clock division ratio to produce 400-khz clock signals to be supplied to the dtmf generation circuit. the division ratio determines the counter value of 6b'000101 to 6b'110011(d'5 to d'51) according to the range 2.0 to 20.4 mhz. 000000: setting prohibited 000001: setting prohibited 000010: setting prohibited 000011: setting prohibited 000100: setting prohibited 000101: division ratio (5) main clock frequency (2.0 mhz) 000110: division ratio (6) main clock frequency (2.4 mhz) 000111: division ratio (7) main clock frequency (2.8 mhz) : : 110001: division ratio (49) main clock frequency (19.6 mhz) 110010: division ratio (50) main clock frequency (20.0 mhz) 110011: division ratio (51) main clock frequency (20.4 mhz) 110100: setting prohibited : : 111111: setting prohibited note: the correct values should be set in dtl0 to dtl5. if these bit settings do not match the system clock, correct dtmf signal output frequency cannot be obtained. additionally, correct operation is not guaranteed if the dtl0 to dtl5 settings are other than 5 to 51 (division ratio 5 to 51).
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 497 of 656 rej09b0071-0500 18.4 operation 18.4.1 output waveform the dtmf generation circuit provides synthesized row and column groups output waveforms or sine waveforms (dtcr signal) of row or column group from toned pin. these signals are produced in the high-precision resistor rudder-type d/a converter. the output frequency is set in dtcr. figure 18.3 shows the toned pin output equivalent circuit. figure 18.4 shows a single output waveform of column or row group alone. one cycle of the output waveform is divided into 32, resulting in low-distortion stable signal waveforms. control output control row column av cc av ss toned figure 18.3 toned pin output equivalent circuit time slot av cc av ss 12345678 9 1011121314151617181 9 202122232425 3031 32 2627282 9 figure 18.4 toned pin output waveform (row or column group alone) table 18.2 shows dtmf generation circuit output signal and typical signal frequencies, and frequency deviation between the two.
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 498 of 656 rej09b0071-0500 table 18.2 frequency deviation between dtmf output signals and typical signals symbol typical signal (hz) dtmf signal output (hz) frequency deviation (%) r1 697 694.44 ? 0.37 r2 770 769.23 ? 0.10 r3 852 851.06 ? 0.11 r4 941 938.97 ? 0.22 c1 1209 1212.12 0.26 c2 1336 1333.33 ? 0.20 c3 1477 1481.48 0.30 c4 1633 1639.34 0.39 18.4.2 operation flow the operating procedure for the dtmf generation circuit is as follows: 1. set the system clock division ratio for the dtlr based on the frequency of the connected system clock. (2.0 to 20.4 mhz, with 400-khz steps) 2. set the frequencies of the row (r1 to r4) and column (c1 to c4) sections based on clf0, clf1, rwf0 and rwf1 of the dtcr. 3. select the outputs of the row and column based on cloe and rwoe of the dtcr, and set dten to 1 to operate the dtmf generation circuit. with the above setting, the set dtmf signal is output from the toned pin.
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 499 of 656 rej09b0071-0500 18.5 application circuit example an application example of the dtmf generation circuit is shown in figure 18.5. toned av cc lsi pxx dtmf v ref 1 ha16808ant mute 2sc458 1 9 2 k 24 k 100 k 360 k +0.47 f 20 11 note: the numeric values on the right end of the signal lines indicate the ha16808ant pin numbers. figure 18.5 example of ha16808ant connection 18.6 usage notes 1. setting the module stop mode it is possible to enable/disable the dtmf operation using the module stop control register. the dtmf does not operate by the initial value of the register. the register can be accessed by releasing the module stop mode. for more details, see section 22, power-down modes. 2. dtlr setting and system clock when using the dtmf generation circuit, note the following: the dtlr must be set so as to accommodate the system clock. if the dtlr setting does not match the system clock, correct dtmf signal output frequency cannot be obtained. 3. relationship between avcc, avss and vcc, vss set avss = vss as the relationship between avcc, avss and vcc, vss. if the dtmf generation circuit is not used, the avcc and avss pins must not be left open. note: if the conditions above are not met, the reliability of the device may be adversely affected.
section 18 dtmf generation circuit rev. 5.00 sep. 01, 2009 page 500 of 656 rej09b0071-0500
section 19 ram rev. 5.00 sep. 01, 2009 page 501 of 656 rej09b0071-0500 section 19 ram the h8s/2268 group and the h8s/2264 group have on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabli ng one-state access by the cpu to both byte data and word data. product classification ram size ram address h8s/2268f 16 kbytes h'ffb000 to h'ffefbf, h'ffffc0 to h'ffffff h8s/2266f 8 kbytes h'ffd000 to h'ffefbf, h'ffffc0 to h'ffffff flash memory version h8s/2265f 4 kbytes h'ffe000 to h'ffefbf, h'ffffc0 to h'ffffff masked rom version h8s/2264 4 kbytes h'ffe000 to h'ffefbf, h'ffffc0 to h'ffffff h8s/2262 2 kbytes h'ffe800 to h'ffefbf, h'ffffc0 to h'ffffff
section 19 ram rev. 5.00 sep. 01, 2009 page 502 of 656 rej09b0071-0500
section 20 rom rev. 5.00 sep. 01, 2009 page 503 of 656 rej09b0071-0500 section 20 rom the features of the flash memory are summarized below. the block diagram of the flash memory is shown in figure 20.1. 20.1 features ? size product type rom size rom address h8s/2268f 256 kbytes h'000000 to h'03ffff h8s/2266f 128 kbytes h'000000 to h'01ffff h8s/2265f 128 kbytes h'000000 to h'01ffff ? programming/erase methods the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory of the h8s/2268 is configured as follows: 64 kbytes 3 blocks, 32 kbytes 1 block, and 4 kbytes 8 blocks. the flash memory of the h8s/2266 and h8s/2265 is configured as follows: 64 kbytes 1 block, 32 kbytes 1 block, and 4 kbytes 8 blocks. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability the flash memory can be reprogrammed for 100 times. ? two programming modes boot mode user program mode on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? automatic bit rate adjustment for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection there are three protect modes, hardware, soft ware, and error protect, which allow protected status to be designated for flash memory program/erase operations. romf253b_000020030700
section 20 rom rev. 5.00 sep. 01, 2009 page 504 of 656 rej09b0071-0500 ? programmer mode flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? emulation function for flash memory in ram the real-time emulation for programming of flash memory is possible by overlapping the flash memory to a part of ram. module bus bus interface/controller flash memory operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 erase block register 2 ram emulation register legend: flmcr1: flmcr2: ebr1: ebr2: ramer: flpwcr: flash memory power control register flpwcr figure 20.1 block diagram of flash memory 20.2 mode transitions when the mode pins and the fwe pin are set in th e reset state and a reset-start is executed, this lsi enters an operating mode as shown in figure 20.2. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory.
section 20 rom rev. 5.00 sep. 01, 2009 page 505 of 656 rej09b0071-0500 the differences between boot mode and user program mode are shown in table 20.1. figure 20.3 shows the operation flow for boot mode and figure 20.4 shows that for user program mode. boot mode on-board programming mode user program mode user mode reset state programmer mode res = 0 fwe = 1 fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. md1 = 0, md2 = 0, p14 = 0, p16 = 0, p70 = 1 res = 0 md1 = 0 md2 = 1, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 20.2 flash memory state transitions table 20.1 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * program/program-verify progr am/program-verify/erase/ erase-verify/emulation note: * to be provided by the user, in accordance with the recommended algorithm.
section 20 rom rev. 5.00 sep. 01, 2009 page 506 of 656 rej09b0071-0500 flash memory this lsi ram host programming control program sci application program (old version) new application program flash memory this lsi ram host sci application program (old version) boot program area new application program flash memory this lsi ram host sci flash memory preprogramming erase boot program new application program flash memory this lsi program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in this lsi (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program figure 20.3 boot mode
section 20 rom rev. 5.00 sep. 01, 2009 page 507 of 656 rej09b0071-0500 flash memory this lsi ram host programming/ erase control program sci boot program new application program flash memory this lsi ram host sci new application program flash memory this lsi ram host sci flash memory erase boot program new application program flash memory this lsi program execution state ram host sci boot program boot program fwe assessment program application program (old version) new application program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program figure 20.4 user program mode (example)
section 20 rom rev. 5.00 sep. 01, 2009 page 508 of 656 rej09b0071-0500 20.3 block configuration figure 20.5 shows the block configuration of 256-kbyte flash memory of the h8s/2268. figure 20.6 shows the block configuration of 128-kbyte flash memory of the h8s/2266 and h8s/2265. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory of the h8s/2268 is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (3 blocks). the flash memory of the h8s/2266 and h8s/2265 is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (1 block). erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80.
section 20 rom rev. 5.00 sep. 01, 2009 page 509 of 656 rej09b0071-0500 eb0 erase unit 4 kbytes eb1 erase unit 4 kbytes eb2 erase unit 4 kbytes eb3 erase unit 4 kbytes eb4 erase unit 4 kbytes eb5 erase unit 4 kbytes eb6 erase unit 4 kbytes eb7 erase unit 4 kbytes eb8 erase unit 32 kbytes eb 9 erase unit 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 programming unit: 128 bytes programming unit: 128 bytes eb10 erase unit 64 kbytes h'02007f h'02ffff h'020000 h'020001 h'020002 programming unit: 128 bytes eb11 erase unit 64 kbytes h'03007f h'03ffff h'030000 h'030001 h'030002 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 20.5 flash memory block configuration (h8s/2268)
section 20 rom rev. 5.00 sep. 01, 2009 page 510 of 656 rej09b0071-0500 eb0 erase unit 4 kbytes eb1 erase unit 4 kbytes eb2 erase unit 4 kbytes eb3 erase unit 4 kbytes eb4 erase unit 4 kbytes eb5 erase unit 4 kbytes eb6 erase unit 4 kbytes eb7 erase unit 4 kbytes eb8 erase unit 32 kbytes eb 9 erase unit 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 20.6 flash memory block configuration (h8s/2266 and h8s/2265)
section 20 rom rev. 5.00 sep. 01, 2009 page 511 of 656 rej09b0071-0500 20.4 input/output pins the flash memory is controlled by means of the pins shown in table 20.2. table 20.2 pin configuration pin name i/o function res input reset fwe input flash program/erase protection by hardware md2 input sets this lsi?s operating mode md1 input sets this lsi?s operating mode p70 input sets mcu operating mode in programmer mode p16 input sets mcu operating mode in programmer mode p14 input sets mcu operating mode in programmer mode txd0 output serial transmit data output rxd0 input serial receive data input 20.5 register descriptions the flash memory has the following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? erase block register 2 (ebr2) ? ram emulation register (ramer) ? flash memory power control register (flpwcr) ? serial control register x (scrx) the registers described above are not present in the masked rom version. if a register described above is read in the masked rom versi on, an undefined value will be returned.
section 20 rom rev. 5.00 sep. 01, 2009 page 512 of 656 rej09b0071-0500 20.5.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 20.8, flash memory programming/erasing. bit bit name initial value r/w description 7 fwe ? r flash write enable bit reflects the input level at the fwe pin. it is cleared to 0 when a low level is input to the fwe pin, and set to 1 when a high level is input. when this bit is cleared to 0, the flash memory changes to hardware protect mode. 6 swe1 0 r/w software write enable bit when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, bits 5 to 0 in flmcr1 register and all ebr1 and ebr2 bits cannot be set. [setting condition] when fwe = 1. 5 esu1 0 r/w erase setup bit when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e1 bit in flmcr1. [setting condition] when fwe = 1 and swe1 = 1 4 psu1 0 r/w program setup bit when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p1 bit in flmcr1. [setting condition] when fwe = 1 and swe1 = 1 3 ev1 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. [setting condition] when fwe = 1 and swe1 = 1
section 20 rom rev. 5.00 sep. 01, 2009 page 513 of 656 rej09b0071-0500 bit bit name initial value r/w description 2 pv1 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program- verify mode is cancelled. [setting condition] when fwe = 1 and swe1 = 1 1 e1 0 r/w erase when this bit is set to 1, and while the swe1 and esu1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. [setting condition] when fwe = 1, swe1 = 1, and esu1 = 1 0 p1 0 r/w program when this bit is set to 1, and while the swe1 and psu1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. when fwe = 1, swe1 = 1, and psu1 = 1 20.5.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see section 20.9.3, error protection, for details. 6 to 0 ? all 0 r reserved these bits are always read as 0.
section 20 rom rev. 5.00 sep. 01, 2009 page 514 of 656 rej09b0071-0500 20.5.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase area block. ebr1 is initialized to h'00 when the swe1 bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 and ebr2 to be automatically cleared to 0. bit bit name initial value r/w description 7 eb7 0 r/w when this bit is set to 1, 4 kbytes of eb7 (h'007000 to h'007fff) will be erased. 6 eb6 0 r/w when this bit is set to 1, 4 kbytes of eb6 (h'006000 to h'006fff) will be erased. 5 eb5 0 r/w when this bit is set to 1, 4 kbytes of eb5 (h'005000 to h'005fff) will be erased. 4 eb4 0 r/w when this bit is set to 1, 4 kbytes of eb4 (h'004000 to h'004fff) will be erased. 3 eb3 0 r/w when this bit is set to 1, 4 kbytes of eb3 (h'003000 to h'003fff) will be erased. 2 eb2 0 r/w when this bit is set to 1, 4 kbytes of eb2 (h'002000 to h'002fff) will be erased. 1 eb1 0 r/w when this bit is set to 1, 4 kbytes of eb1 (h'001000 to h'001fff) will be erased. 0 eb0 0 r/w when this bit is set to 1, 4 kbytes of eb0 (h'000000 to h'000fff) will be erased.
section 20 rom rev. 5.00 sep. 01, 2009 page 515 of 656 rej09b0071-0500 20.5.4 erase block register 2 (ebr2) ebr2 specifies the flash memory erase area block. ebr2 is initialized to h'00 when the swe1 bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 and ebr2 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 4 ? all 0 r/w reserved these bits are always read as 0. only 0 should be written to these bits. 3 eb11 * 0 r/w when this bit is set to 1, 64 kbytes of eb11 (h'030000 to h'03ffff) will be erased. 2 eb10 * 0 r/w when this bit is set to 1, 64 kbytes of eb10 (h'020000 to h'02ffff) will be erased. 1 eb9 0 r/w when this bit is set to 1, 64 kbytes of eb9 (h'010000 to h'01ffff) will be erased. 0 eb8 0 r/w when this bit is set to 1, 32 kbytes of eb8 (h'008000 to h'00ffff) will be erased. note: * these bits are reserved bits in the h8s/2266 and h8s/2265. only 0 should be written to these bits. 20.5.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer settings should be made in user mode or user program mode. to ensure correct operation of the emulation function, the rom for which ram emulation is performed sh ould not be accessed immedi ately after this regist er has been modified. normal execution of an access immediately afte r register modificati on is not guaranteed. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. 4 ? 0 r/w reserved only 0 should be written to this bit.
section 20 rom rev. 5.00 sep. 01, 2009 page 516 of 656 rej09b0071-0500 bit bit name initial value r/w description 3 rams 0 r/w ram select specifies selection or non-selection of flash memory emulation in ram. when rams = 1, the flash memory is overlapped with part of ram, and all flash memory block are program/erase-protected. 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area selection when the rams bit is set to 1, one of the following flash memory areas is selected to overlap the ram area. the areas correspond with 4-kbyte erase blocks. 000: h'000000 to h'000fff (eb0) 001: h'001000 to h'001fff (eb1) 010: h'002000 to h'002fff (eb2) 011: h'003000 to h'003fff (eb3) 100: h'004000 to h'004fff (eb4) 101: h'005000 to h'005fff (eb5) 110: h'006000 to h'006fff (eb6) 111: h'007000 to h'007fff (eb7) 20.5.6 flash memory power control register (flpwcr) flpwcr enables/disables transition to power-down modes for the flash memory when this lsi enters sub-active mode. bit bit name initial value r/w description 7 pdwnd 0 r/w power down disable enables/disables transition to power-down modes for the flash memory when this lsi enters sub-active mode. 0: transition to power-down modes for the flash memory enabled. 1: transition to power-down modes for the flash memory disabled. 6 to 0 ? all 0 r reserved these bits are always read as 0.
section 20 rom rev. 5.00 sep. 01, 2009 page 517 of 656 rej09b0071-0500 20.5.7 serial control register x (scrx) scrx performs register access control. bit bit name initial value r/w description 7 ? 0 r/w reserved only 0 should be written to this bit. 6 5 iicx1 iicx0 0 0 r/w r/w i 2 c transfer select 1, 0 for details, see section 14.3.5, serial control register x (scrx). 4 iice 0 r/w i 2 c master enable for details, see section 14.3.5, serial control register x (scrx). 3 flshe 0 r/w flash memory control register enable controls for the cpu accessing to the control registers (flmcr1, flmcr2, ebr1, ebr2) of the flash memory. when this bit is set to 1, the flash memory control registers can be read/written to. when this bit is cleared to 0, the flash memory control registers are not selected. at this time, the contents of the flash memory control registers are retained. 0: area at h'ffffa8 to h'ffffac not selected for the flash memory control registers. 1: area at h'ffffa8 to h'ffffac selected for the flash memory control registers. 2 to 0 ? all 0 r/w reserved only 0 should be written to these bits.
section 20 rom rev. 5.00 sep. 01, 2009 page 518 of 656 rej09b0071-0500 20.6 on-board programming modes when pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 20.3. for a diagram of the transitions to the various flash memory modes, see figure 20.2. table 20.3 setting on-board programming modes fwe md2 md1 mode setting 1 1 0 boot mode 1 1 1 user program mode 0 1 1 user mode 20.6.1 boot mode table 20.4 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 20.8, flash memory programming/erasing. in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 2. sci_0 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci_0 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between
section 20 rom rev. 5.00 sep. 01, 2009 page 519 of 656 rej09b0071-0500 the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 20.5. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'ffc000 to h'ffdfff is the area to which the programming control program is transferred from the host. in the h8s/2266 and h8s/2265, the ram in this area is enabled only in boot mode. the boot program area cannot be used un til the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci_0 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high. the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release * . boot mode is also cleared when a wdt overflow occurs. 8. all interrupts are disabled during programming or erasing of the flash memory. note: * the input signals on the fwe and mode pins must satisfy the mode programming setup time (t mds = 200 ns) at the reset release timing.
section 20 rom rev. 5.00 sep. 01, 2009 page 520 of 656 rej09b0071-0500 table 20.4 boot mode operation item host operation communications contents lsi operation boot mode start branches to boot program at reset-start. processing contents processing contents bit rate adjustment continuously transmits data h'00 at specified bit rate. h'00, h'00 ...... h'00 h'00 h'55 measures low-level period of receive data h'00. calculates bit rate and sets it in brr of sci_0. transmits data h'00 to host as adjustment end indication. transmits data h'aa to host when data h'55 is received. transmits data h'55 when data h'00 is received error-free. transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) receives data h'aa. transmits 1-byte of programming control program (repeated for n times) receives data h'aa. transfer of programming control program flash memory erase execution of programming control program boot program initiation echobacks the 2-byte data received. branches to programming control program transferred to on-chip ram and starts execution. echobacks received data to host and also transfers it to ram (repeated for n times) checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) high-order byte and low-order byte h'xx h'aa echoback echoback h'ff h'aa boot program erase error table 20.5 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency range of this lsi 19,200 bps 8 to 20.5 mhz 9,600 bps 4 to 20.5 mhz 4,800 bps 2 to 20.5 mhz
section 20 rom rev. 5.00 sep. 01, 2009 page 521 of 656 rej09b0071-0500 20.6.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must prepare on- board means for controlling fwe, on-board means of supplying programming data, and branching conditions. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, tr ansfer the user program/erase control program to on-chip ram, as in boot mode. figure 20.7 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 20.8, flash memory programming/erasing. ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 20.7 programming/erasing flowchart example in user program mode
section 20 rom rev. 5.00 sep. 01, 2009 page 522 of 656 rej09b0071-0500 20.7 flash memory emulation in ram a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. emulation can be performed in user mode or user program mode. figure 20.8 shows an example of emulation of real-time flash memory programming. 1. set ramer to overlap part of ram onto the area for which real-time programming is required. 2. emulation is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, thus releasing the ram overlap. 4. the data written in the overlapping ram is written into the flash memory space. start of emulation program set ramer write tuning data to overlap ram execute application program tuning ok? clear ramer write to flash memory emulation block end of emulation program no ye s figure 20.8 flowchart for flash memory emulation in ram
section 20 rom rev. 5.00 sep. 01, 2009 page 523 of 656 rej09b0071-0500 an example in which flash memory block area eb0 is overlapped is shown in figure 20.9. 1. the ram area to be overlapped is fixed at a 4-kbyte area in the range h'ffd000 to h'ffdfff. in the h8s/2265, the ram in this area is enabled only in ram emulation mode. 2. the flash memory area to be overlapped is selected by ramer from a 4-kbyte area of the eb0 to eb7 blocks. 3. the overlapped ram area can be accessed fro m both the flash memory addresses and ram addresses. 4. when the rams bit in ramer is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). in this state, setting the p1 or e1 bit in flmcr1 to 1 does not cause a transition to program mode or erase mode. 5. a ram area cannot be erased by execution of software in accordance with the erase algorithm. 6. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram.
section 20 rom rev. 5.00 sep. 01, 2009 page 524 of 656 rej09b0071-0500 h'000000 h'001000 h'002000 h'003000 h'ffd000 h'ffdfff flash memory (eb0) flash memory (eb0) (eb1) (eb2) (eb3) on-chip ram (4 kbytes) on-chip ram (shadow of h'ffd000 to h'ffdfff) flash memory (eb2) on-chip ram (4 kbytes) (eb3) normal memory map ram overlap memory map figure 20.9 example of ram overlap operation 20.8 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 20.8. 1, program/program-verify and section 20.8.2, erase/erase-verify, respectively.
section 20 rom rev. 5.00 sep. 01, 2009 page 525 of 656 rej09b0071-0500 20.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 20.10 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computati on and additional programming data computation according to figure 20.10. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p1 bit is set to 1 is the programming time. figure 20.10 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. set a value greater than (tspsu + tsp200 + tcp + tcpsu) s as the wdt overflow period. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in words from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is (n).
section 20 rom rev. 5.00 sep. 01, 2009 page 526 of 656 rej09b0071-0500 start end of programming set swe1 bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) 1 s sub-routine write pulse end sub set psu1 bit in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 99 8 999 1000 note 6: write pulse width write time (tsp30/tsp200) s 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) 50 s set p1 bit in flmcr1 wait t sp10 or 30 or 200 clear p1 bit in flmcr1 wait (t cp ) 5 s clear psu1 bit in flmcr1 wait (t cpsu ) 5 s n = 1 m = 0 no no no no yes yes yes wait (t spv ) 4 s t spvr = wait 2 s * 2 * 4 start of programming end of programming * 5 * 1 wait (t cpv ) s apply write pulse t sp 30 or 200 sub-routine-call set pv1 bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv1 bit in flmcr1 clear swe1 bit in flmcr1 m = 1 reprogram see note 6 for pulse width m = 0 ? increment address programming failure yes clear swe1 bit in flmcr1 wait (t cswe ) 100 s no yes 6 n? no yes 6 n ? wait (t cswe ) 100 s n 1000? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: * use a 10 s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area apply write pulse (additional programming) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is ng. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing addit ional data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. 5. a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing of additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. * * * * * * figure 20.10 program/pr ogram-verify flowchart
section 20 rom rev. 5.00 sep. 01, 2009 page 527 of 656 rej09b0071-0500 20.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 20.11 should be followed. 1. prewriting (setting erase block data to all 0) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register 1 and 2 (ebr1 and ebr2). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e1 bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. set a value greater than (t sesu + t se + t ce + t cesu ) ms as the wdt overflow period. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in words from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is (n). 20.8.3 interrupt handling when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
section 20 rom rev. 5.00 sep. 01, 2009 page 528 of 656 rej09b0071-0500 erase start set ebr1 (2) enable wdt disable wdt read verify data increment address verify data = all 1? last address of block? all erase block erased? set block start address as verify address h'ff dummy write to verify address swe1 bit in flmcr1 1 n = 1 esu1 bit in flmcr1 1 e1 bit in flmcr1 1 start erasing stop erasing tsswe: wait 1 s tsesu: wait 100 s e1 bit in flmcr1 0 ev1 bit in flmcr1 1 tse: wait 10 ms esu1 bit in flmcr1 0 tce: wait 10 s tcesu: wait 10 s tsev: wait 20 s ev1 bit in flmcr1 0 n n + 1 tcev: wait 4 s swe1 bit in flmcr1 0 tcswe: wait 100 s ev1 bit in flmcr1 0 n 100? tcev: wait 4 s swe1 bit in flmcr1 0 tcswe: wait 100 s erase failure end of erasing tsevr: wait 2 s no yes ye s no no no ye s ye s * 1 * 3 * 2 * 4 erasing should be done to a block 1. pre-writing (all erase block data are cleared to 0) is not necessary. 2. verify data is read out in 16 bit size (word access). 3. erasing block register (ebr) can be set about 1 bit at a time. do not specify 2 bits or more. 4. erasing is performed block by block. when multiple blocks must be erased, erase each lock one by one. notes: figure 20.11 erase/erase-verify flowchart
section 20 rom rev. 5.00 sep. 01, 2009 page 529 of 656 rej09b0071-0500 20.9 program/erase protection there are three kinds of flash memory program/er ase protection; hardware protection, software protection, and error protection. 20.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and erase block register 2 (ebr2) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 20.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe1 bit in flmcr1. when software protection is in effect, setting the p1 or e1 bit in flmcr1 does not cause a transition to pr ogram mode or erase mode. by setting the erase block register 1 and 2 (ebr1 and ebr2), erase protection can be set for individual blocks. when ebr1 and ebr2 are set to h'00, erase protection is set for all blocks. by setting bit rams in ramer, programming/erase protection is set for all blocks. 20.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operati on is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling (excluding a reset) during programming/erasing ? when a sleep instruction is executed during programming/erasing ? when the cpu loses the bus during programming/erasing
section 20 rom rev. 5.00 sep. 01, 2009 page 530 of 656 rej09b0071-0500 the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p1 or e1 bit. however, pv1 and ev1 bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a reset or in hardware standby. 20.10 interrupt handling when progr amming/erasing flash memory all interrupts, including nmi input, are disabled when flash memory is being programmed or erased (when the p1 or e1 bit is set in flmcr1), and while the boot program is executing in boot mode * 1 , to give priority to the program or eras e operation. there are three reasons for this: 1. interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly * 2 , possibly resulting in cpu runaway. 3. if an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. notes: 1. interrupt requests must be disabled inside and outside the cpu until the programming control program has completed programming. 2. the vector may not be read correctly in this case for the following two reasons: ? if flash memory is read while being programmed or erased (while the p1 or e1 bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). ? if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 20.11 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. use a prom programmer which supports the renesas 256-kbyte flash memory on-chip microcomputer device type (fztat256v3a). the socket adapter pin correspondence diagram is shown in figure 20.12.
section 20 rom rev. 5.00 sep. 01, 2009 page 531 of 656 rej09b0071-0500 this lsi socket adapter (conversion to 40-pin arrangement) fp-100b,tfp-100b, tfp-100g pin no. pin name a0 a1 a2 a3 a4 a5 a6 a7 a8 a 9 a10 a11 a12 a13 a14 a15 a16 a17 a18 d0 d1 d2 d3 d4 d5 d6 d7 ce oe we fwe hn27c40 9 6hg (40-pin) pin no. pin name 21 22 23 24 25 26 27 28 2 9 31 32 33 34 35 36 37 38 3 9 10 1 9 18 17 16 15 14 13 12 2 20 3 4 1, 40 11, 30 5, 6, 7 8 9 a0 a1 a2 a3 a4 a5 a6 a7 a8 a 9 a10 a11 a12 a13 a14 a15 a16 a17 a18 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 ce oe we fwe v cc v ss nc a20 a1 9 r e s xtal extal n.c.(open) 17 16 15 13 11 10 9 8 7 6 5 4 3 2 1 100 99 9 8 9 7 25 24 23 22 21 20 1 9 18 26 28 27 66 5 9 63 65 other than the above 12, 30, 53, 54, 58, 60, 61, 62, 75 14, 2 9 , 38, 40,42, 56, 64, 67 v cc v ss oscillator circuit legend: fwe: i/o0 to 7: a20 to 0: oe : ce : we : flash write enable data input/output address input output enable chip enable write enable power-on reset circuit note: this drawing indicates pin correspondences and does not show the entire circuitry of the socket adapter. figure 20.12 socket adap ter pin correspondence diagram
section 20 rom rev. 5.00 sep. 01, 2009 page 532 of 656 rej09b0071-0500 20.12 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to at high speed. ? power-down state the flash memory can be read when part of the power circuit is halted and the lsi operates by subclocks. ? standby mode all flash memory circuits are halted. table 20.6 shows the correspondence between the operating modes of the h8s/2268 group and the flash memory. when the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 100 s, even when the external clock is being used. table 20.6 flash memory operating states lsi operating state flash memory operating state active mode normal operating mode sleep mode normal operating mode watch mode standby mode standby mode sub-active mode sub-sleep mode pdwnd = 0: power-down mode (read only) pdwnd = 1: normal operating mode (read only)
section 20 rom rev. 5.00 sep. 01, 2009 page 533 of 656 rej09b0071-0500 20.13 flash memory programming and erasing precautions precautions concerning the use of on-board prog ramming mode, the ram emulation function, and programmer mode are summarized below. use the specified voltages and timing for programming and erasing: applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the renesas 256-kbyte flash memory on-chip microcomputer device type (fztat256v3a). do not select the hn27c4096 setting for the prom programmer, and only use the specified socket adapter. failure to observe these points may result in damage to the device. powering on and off (see figures 20.13 to 20.15): do not apply a high level to the fwe pin until vcc has stabilized. also, drive the fwe pin low before turning off vcc. when applying or disc onnecting vcc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. fwe application/disconnection (see figures 20.13 to 20.15): fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply fwe when the vcc voltage has stabilized within its rated voltage range. ? in boot mode, apply and disconnect fwe during a reset. ? in user program mode, fwe can be switched between high and low level regardless of the reset state. fwe input can also be switched during execution of a program in flash memory. ? do not apply fwe if program runaway has occurred. ? disconnect fwe only when the swe1, esu1, psu1, ev1, pv1, p1, and e1 bits in flmcr1 are cleared. make sure that the swe1, esu1, psu1, ev1, pv1, p1, and e1 bits are not set by mistake when applying or disconnecting fwe.
section 20 rom rev. 5.00 sep. 01, 2009 page 534 of 656 rej09b0071-0500 do not apply a constant high level to the fwe pin: apply a high level to the fwe pin only when programming or erasing flash memory. a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. use the recommended algorithm when pr ogramming and erasi ng flash memory: the recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. when setting the p1 or e1 bit in flmcr1, the watchdog timer should be set before hand as a precaution against program runaway, etc. do not set or clear the swe1 bit during execution of a program in flash memory: wait for at least 100 s after clearing the swe1 bit before executing a program or reading data in flash memory. when the swe1 bit is set, data in flash memo ry can be rewritten. access flash memory only for verify operations (verification during programming/erasing). also, do not clear the swe1 bit during programming, erasing, or verifying. similarly, when using the ram emulation function while a high level is being input to the fwe pin, the swe1 bit must be cleared before executing a program or reading data in flash memory. however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe1 bit is set or cleared. do not use interrupts while flash memory is being programmed or erased: all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations. do not perform additional programming. erase the memory before reprogramming: in on- board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, too, perfor m only one programming operation on a 128-byte programming unit block. programming should be carried out with the entire programming unit block erased. before programming, check that the chip is correctly mounted in the prom programmer: overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned.
section 20 rom rev. 5.00 sep. 01, 2009 page 535 of 656 rej09b0071-0500 do not touch the socket adapter or chip during programming: touching either of these can cause contact faults and write errors. reset the flash memory be fore turning on the power: to reset the flash memory during oscillation stabilization period, the reset signal must be input for at least 100 s. apply the reset signal while swe1 is low to reset the flash memory during its operation: the reset signal is applied at least 100 s after the swe1 bit has been cleared. 1. 2. 3. except when switching modes, the level of the mode pins (md2, md1) must be fixed until power-off by pulling the pins up or down. see section 25.2.8, flash memory characteristics. mode programming setup time t mds (min.) = 200ns. period during which flash memory access is prohibited (t sswe : wait time after setting swe1 bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: v cc fwe t osc1 min 0 s min 0 s t mds * 3 t mds * 3 md2, md1 * 1 r e s swe1bit swe1 set swe1 cleared t sswe 100 s programming/ erasing possible wait time: wait time: figure 20.13 power-on/off timing (boot mode)
section 20 rom rev. 5.00 sep. 01, 2009 page 536 of 656 rej09b0071-0500 swe1 set swe1 cleared v cc fwe t osc1 min 0 s md2,md1 * 1 r e s swe1 bit t sswe t mds * 3 100 s 1. 2. 3. except when switching modes, the level of the mode pins (md2, md1) must be fixed until power-off by pulling the pins up or down. see section 25.2.8, flash memory characteristics. mode programming setup time t mds (min.) = 200ns. period during which flash memory access is prohibited (t sswe : wait time after setting swe1 bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: programming/ erasing possible wait time: wait time: figure 20.14 power-on/off timing (user program mode)
section 20 rom rev. 5.00 sep. 01, 2009 page 537 of 656 rej09b0071-0500 v cc fwe t osc1 min 0 s t mds t mds t mds t resw md2, md1 r e s swe1 bit mode change boot mode mode change user mode user program mode user mode user program mode swe1 set swe1 cleared t sswe * 4 * 4 * 4 * 2 1. 2. 3. 4. when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of r e s input. when making a transition from boot mode to another mode, a mode programming setup time t mds (min.) of 200 ns is necessary with respect to r e s clearance timing. see section 25.2.8, flash memory characteristics. wait time: 100 s. period during which flash memory access is prohibited (t sswe : wait time after setting swe1 bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: * 1 * 1 wait time: programming/ erasing possible t sswe wait time: programming/ erasing possible t sswe wait time: programming/ erasing possible t sswe wait time: programming/ erasing possible figure 20.15 mode transition timing (example: boot mode user mode ? user program mode)
section 20 rom rev. 5.00 sep. 01, 2009 page 538 of 656 rej09b0071-0500 20.14 note on switching from f-ztat version to masked rom version the masked rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 20.7 lists the registers that are present in the f-ztat version but not in the masked rom version. if a register listed in table 20.7 is read in the masked rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a masked rom version product, it must be modified to ensure that the registers in table 20.7 have no effect. table 20.7 registers present in f-ztat v ersion but absent in masked rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb flash memory power control register flpwcr h'ffac serial control register x (only bit 3) scrx h'fdb4
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 539 of 656 rej09b0071-0500 section 21 clock pulse generator this lsi has an on-chip clock pulse generator that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator, duty adjustment circuit, clock selection circuit, medium-speed cl ock divider, bus master clock selection circuit, subclock oscillator, and wave formation circuit. a block diagram of the clock pulse generator is shown in figure 21.1. legend: lpwrcr: sckcr: low-power control register system clock control register extal xtal duty adjustment circuit medium- speed clock divider system clock oscillator clock selection circuit sub wdt_1, tmr4, lcd count clock internal clock to peripheral modules bus master cloc k to cpu and dtc /2 to /32 internal clock sck2 to sck0 sckcr rfcut osc1 osc2 waveform generation circuit subclock oscillator lpwrcr bus master clock selection circuit figure 21.1 block diagram of clock pulse generator frequency changes are performed by software by settings in the low-power control register (lpwrcr) and system clock control register (sckcr). cpg0501b_000020020700
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 540 of 656 rej09b0071-0500 21.1 register descriptions the on-chip clock pulse generator has the following registers. ? system clock control register (sckcr) ? low-power control register (lpwrcr) 21.1.1 system clock control register (sckcr) sckcr performs medium-speed mode control. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved these are readable/writable bits, but the write value should always be 0. 5, 4 ? all 0 ? reserved these bits are always read as 0.writing is invalid. 3 ? 0 r/w reserved this is a readable/writable bit, but the write value should always be 0. 2 1 0 sck2 sck1 sck0 0 0 0 r/w r/w r/w system clock select 2 to 0 these bits select the bus master clock. 000: high-speed mode 001: medium-speed clock is /2 010: medium-speed clock is /4 011: medium-speed clock is /8 100: medium-speed clock is /16 101: medium-speed clock is /32 11x: setting prohibited legend: x: don?t care
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 541 of 656 rej09b0071-0500 21.1.2 low-power control register (lpwrcr) lpwrcr performs down-mode control, selects sampling frequency for eliminating noise, performs subclock generation control, and specifies multiplication factor. bit bit name initial value r/w description 7 dton 0 r/w direct transition on flag 0: when the sleep instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode. when the sleep instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. 1: when the sleep instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode, or shifts to sleep mode or software standby mode. when the sleep instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode. 6 lson 0 r/w low speed on fag 0: when the sleep instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . when the sleep instruction is executed in sub-active mode, operation shifts to watch mode * or shifts directly to high-speed mode. operation shifts to high-speed mode when watch mode is cancelled. 1: when the sleep instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode. when the sleep instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. operation shifts to sub-active mode when watch mode is cancelled.
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 542 of 656 rej09b0071-0500 bit bit name initial value r/w description 5 nesel 0 r/w noise elimination sampling frequency select this bit selects the sampling frequency of the subclock ( sub ) generated by the subclock oscillator is sampled by the clock ( ) generated by the system clock oscillator set 0 when is 5 mhz or higher. set 1 when is 2.1 mhz or lower. any value can be set when is 2.1 to 5 mhz. 0: sampling using 1/32 1: sampling using 1/4 4 substp 0 r/w subclock enable this bit enables/disables subclock generation. this bit should be set to 1 when subclock is not used. 0: enables subclock generation. 1: disables subclock generation. 3 rfcut 0 r/w oscillation circuit feedback resistance control bit selects whether or not built-in feedback resistance and duty adjustment circuit of the system clock generator are used when an external clock is input. do not access when the crystal resonator is used. after setting this bit in the external clock input state, enter software standby mode, watch mode, or subactive mode. when software standby mode, watch mode, or subactive mode is entered, switch whether or not built-in feedback resistance and duty adjustment circuit are used. 0: built-in feedback resistance and duty adjustment circuit of the system clock generator used. 1: built-in feedback resistance and duty adjustment circuit of the system clock generator not used. 2 ? 0 r/w reserved this is a readable/writable bit, but the write value should always be 0.
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 543 of 656 rej09b0071-0500 bit bit name initial value r/w description 1 0 stc1 stc0 0 0 r/w r/w multiplication factor setting specifies multiplication factor of the pll circuit built in the evaluation chip. the specified multiplication factor becomes valid software standby mode, watch mode, or subactive mode is entered. these bits should be set to 11 in this lsi. since the value becomes stc1 = stc0 = 0 after a reset, set stc1 = stc0 = 1. 00: 1 01: 2 (setting prohibited) 10: 4 (setting prohibited) 11: pll is bypass note: * when watch mode or subactive mode is entered, set high-speed mode. 21.2 system clock oscillator system clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 21.2.1 connecting a crystal resonator a crystal resonator can be connected as shown in the example in figure 21.2. select the damping resistance r d according to table 21.1. an at-cut pa rallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf note: c l1 and c l2 are reference values including the floating capacitance of the board. figure 21.2 connection of crystal resonator (example)
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 544 of 656 rej09b0071-0500 table 21.1 damping resistance value frequency (mhz) 2 4 6 8 10 12 16 20 r d ( ) 1 k 500 300 200 100 0 0 0 figure 21.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 21.2. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 21.3 crystal resonator equivalent circuit table 21.2 crystal resonator characteristics frequency (mhz) 2 4 6 8 10 12 16 20 r s max. ( ) 500 120 100 80 60 60 50 40 c 0 max. (pf) 7 7 7 7 7 7 7 7 21.2.2 external clock input an external clock signal can be input as shown in the examples in figure 21.4. if the xtal pin is left open, ensure that stray capacitance does not exceed 10 pf. when complementary clock is input to the xtal pin, the external clock input should be fixed high in standby mode, subactive mode, subsleep mode, or watch mode. extal xtal extal xtal external clock input open external clock input (a) xtal pin left open (b) complementary clock input at xtal pin figure 21.4 external clock input (examples)
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 545 of 656 rej09b0071-0500 table 21.3 shows the input conditions for the external clock. table 21.4 shows the input conditions for the external clock when duty adjustment circuit is not used. table 21.3 external clock input conditions v cc = 2.7 v to 5.5 v v cc = 4.0 v to 5.5 v item symbol min. max. min. max. unit test conditions external clock input low pulse width t exl 30 ? 20 ? ns external clock input high pulse width t exh 30 ? 20 ? ns external clock rise time t exr ? 7 ? 5 ns figure 21.5 external clock fall time t exf ? 7 ? 5 ns table 21.4 external clock input conditions (duty adjustment circuit not used) v cc = 2.7 v to 5.5 v v cc = 4.0 v to 5.5 v item symbol min. max. min. max. unit test conditions external clock input low pulse width t exl 37 ? 25 ? ns external clock input high pulse width t exh 37 ? 25 ? ns external clock rise time t exr ? 7 ? 5 ns figure 21.5 external clock fall time t exf ? 7 ? 5 ns note: when duty adjustment circuit is not used, maximum operating frequency is lowered according to the input waveform. (example: when t exl = t exh = 50 ns, t exr = t exf = 10 ns, clock cycle time = 120 ns, and maximum operating frequency = 8.3 mhz)
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 546 of 656 rej09b0071-0500 t exh t exl t exr t exf v cc 0.5 extal figure 21.5 external clock input timing 21.2.3 notes on switching external clock when two or more external clocks (e.g.: 10 mhz and 2 mhz) are used as the system clock, input clock should be switched in software standby mode. an example of external clock switching circuit is shown in figure 21.6. an example of external clock switching timing is shown in figure 21.7. this lsi port output external interrupt extal external clock 1 external clock 2 selector control circuit external clock switch request external interrupt signal external clock switch signal figure 21.6 external clock switching circuit (examples)
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 547 of 656 rej09b0071-0500 200ns or more (2) (1) port output (clock switching) (2) transition to software standby mode (3) external clock switchover (4) external interrupt generation (an interrupt should be input 200 ns or more after transition to software standby mode.) (5) interrupt exception handling (5) sleep instruction execution interrupt exception handling operation external clock 1 external clock 2 (1) port output (3) external clock switching circuit extal internal clock (4) standby mode external interrupt active (external clock1) active (external clock2) software standby mode clock switching request figure 21.7 external clock switching timing (examples) 21.3 duty adjustment circuit the duty adjustment circuit is valid when oscillation frequency is more than 5 mhz. the duty adjustment circuit adjusts clock output fr/m the system clock oscillator to generate the system clock ( ). 21.4 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 21.5 bus master clock selection circuit the bus master clock selection circuit selects the clock supplied to the bus master by setting the bits sck2 to sck0 in sckcr. the bus master clock can be selected from system clock ( ), or medium-speed clocks ( /2, /4, /8, /16, /32).
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 548 of 656 rej09b0071-0500 21.6 subclock oscillator 21.6.1 connecting 32.768-khz crystal resonator to supply a clock to the subclock divider, connect a 32.768-khz crystal resonator, as shown in figure 21.8. figure 21.9 shows the equivalence circuit for a 32.768khz oscillator. osc1 osc2 c 1 c 2 c 1 = c 2 = 15 pf (typ.) note: c1 and c2 are reference values including the floating capacitance of the boad. figure 21.8 example connection of 32.768-khz crystal resonator osc1 osc2 c s l s r s c o co = 1.5 pf (typ.) rs = 14 k (typ.) fw = 32.768 khz type name = c001r (seiko epson) figure 21.9 equivalence circuit for 32.768-khz crystal resonator
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 549 of 656 rej09b0071-0500 21.6.2 handling pins when subclock not required if no subclock is required, connect the osc1 pin to vss and leave osc2 open, as shown in figure 21.10. set the substp bit of lpwrcr to 1. osc1 osc2 open note: set the substp bit in lpwrcr to 1. figure 21.10 pin handling when subclock not required 21.7 subclock waveform generation circuit to eliminate noise from the subclock input to osci, the subclock is sampled using the dividing clock . the sampling frequency is set using the nes el bit of lpwrcr. for details, see section 21.1.2, low power control register (lpwrcr). no sampling is performed in sub-active mode, sub-sleep mode, or watch mode. 21.8 usage notes 21.8.1 note on crystal resonator as various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.
section 21 clock pulse generator rev. 5.00 sep. 01, 2009 page 550 of 656 rej09b0071-0500 21.8.2 note on board design when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. make wires as short as possible. other signal lines should be routed away from the oscillator circuit, as shown in figure 21.11. this is to prevent induction from interfering with correct oscillation. c2 avoid signal a signal b c1 this lsi xtal, osc2 extal, osc1 figure 21.11 note on board design of oscillator circuit 21.8.3 note on using a crystal resonator when a microcomputer runs, internal power suppl y potential will fluctuate synchronized with the system clock. in addition, according to the individual characteristics of crystal resonator, there is a case where the amplitude of the oscillation waveform will not be grown sufficiently immediately after oscillation stabilization period, thus the oscillation waveform is easily affected by the fluctuation of the power supply voltage. in this condition, oscillation waveform will be unstable, resulting in the system clock instability and malfunction of the microcomputer. if a malfunction occurs, the setting of the standby timer select 2 to 0 (sts2 to sts0) bits in the standby control register (sbycr) must be set so as for the standby time to be longer. for example, if a malfunction occurs when the standby time is set to 8192 states, the operation should be confirmed by setting the sta ndby time to 16384 states or longer. in addition, if a malfunction similar to at state transition occurs at reset, the res pin hold time must be set longer.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 551 of 656 rej09b0071-0500 section 22 power-down modes in addition to the normal progr am execution state, the h8s/2268 group and the h8s/2264 group have nine power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip peripheral modules, and so on. the h8s/2268 group and the h8s/2264 group operating modes are as follows: 1. high-speed mode 2. medium-speed mode 3. subactive mode 4. sleep mode 5. subsleep mode 6. watch mode 7. module stop mode 8. software standby mode 9. hardware standby mode 2. to 9. are low power dissipation states. sleep mode and sub-sleep mode are cpu states, medium- speed mode is a cpu and bus master state, sub-active mode is a cpu and bus master and internal peripheral function state, and module stop mode is an internal peripheral function (including bus masters other than the cpu) state. so me of these states can be combined. after a reset, the lsi is in high-speed mode with modules other than the dtc in module stop mode. table 22.1 shows the internal state of the lsi in the respective modes. table 22.2 shows the conditions for shifting between the low power dissipation modes. figure 22.1 is a mode transition diagram.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 552 of 656 rej09b0071-0500 table 22.1 lsi internal states in each mode function high- speed medium- speed sleep module stop watch sub- active subsleep software standby hardware standby system clock pulse generator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock pulse generator function- ing/halted function- ing/halted function- ing/halted function- ing/halted function- ing function- ing function- ing function- ing/halted halted cpu instructions halted halted halted halted halted registers function- ing medium- speed operation retained function- ing retained subclock operation retained retained undefined ram function- ing function- ing function- ing (dtc) * 2 function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing function- ing halted high impedance external interrupts nmi irqn wkpn function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted peripheral functions pbc * 2 function- ing medium- speed operation function- ing function- ing/halted (retained) halted (retained) subclock operation halted (retained) halted (retained) halted (reset) dtc * 2 function- ing medium- speed operation function- ing function- ing/halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) tmr_4 * 2 lcd function- ing function- ing function- ing function- ing/halted (retained) subclock operation * 1 subclock operation * 1 subclock operation * 1 halted (retained) halted (reset) wdt_1 function- ing function- ing function- ing function- ing subclock operation * 1 subclock operation * 1 subclock operation * 1 halted (retained) halted (reset) wdt_0 function- ing function- ing function- ing function- ing halted (retained) subclock operation subclock operation halted (retained) halted (reset) tmr_0 tmr_1 tmr_2 * 2 tmr_3 * 2 function- ing function- ing function- ing function- ing/halted (retained) halted (retained) subclock operation subclock operation halted (retained) halted (reset) tpu sci iic dtmf * 2 d/a * 2 * 3 function- ing function- ing function- ing function- ing/halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) a/d function- ing function- ing function- ing function- ing/halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset)
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 553 of 656 rej09b0071-0500 notes: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 1. when the tmr_4 * 2 , wdt_1, or lcd is operated in watch, subactive, or subsleep mode, use the subclock. 2. supported only by the h8s/2268 group. 3. "halted (retained)" means that internal register values are retained. for analog outputs, the given d/a absolute accuracy is not satisfies because the internal state is "operation suspended."
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 554 of 656 rej09b0071-0500 program-halted state program execution state sck2 to sck0= 0 sck2 to sck0 0 sleep instruction ssby = 1, pss = 1 dton = 1, lson = 1 clock switching exception processing sleep instruction ssby = 1, pss = 1 dton = 1, lson = 0 after the oscillation settling time (sts2 to 0), clock switching exception processing sleep instruction sleep instruction external interrupt * 4 any interrupt * 3 sleep instruction sleep instruction sleep instruction interrupt * 1 lson bit = 0 interrupt * 2 interrupt * 1 lson bit = 1 stby pin = high res pin = low stby pin = low ssby= 0, lson= 0 ssby= 1, pss= 0, lson= 0 ssby= 0, pss= 1, lson= 1 ssby= 1, pss= 1, dton= 0 res pin = high : transition after exception processing : low power dissipation mode reset state high-speed mode (main clock) medium-speed mode (main clock) sub-active mode (subclock) sub-sleep mode (subclock) hardware standby mode software standby mode sleep mode (main clock) watch mode (subclock) notes: 1. 2. 3. 4. h8s/2268 group: nmi, irq0, irq1, irq3 to irq5, wkp0 to wkp7, wdt1 interrupt, and tmr4 interrupt h8s/2264 group: nmi, irq0, irq1, irq3, irq4, wkp0 to wkp7, and wdt1 interrupt h8s/2268 group: nmi, irq0, irq1, irq3 to irq5, wkp0 to wkp7, wdt0 interrupt, wdt1 interrupt, and tmr0 to tmr4 interrupts h8s/2264 group: nmi, irq0, irq1, irq3, irq4, wkp0 to wkp7, wdt0 interrupt, wdt1 interrupt, tmr0 interrupt, and tmr1 interrupt all interrupts h8s/2268 group: nmi, irq0, irq1, irq3 to irq5, wkp0 to wkp7 h8s/2264 group: nmi, irq0, irq1, irq3, irq4, wkp0 to wkp7 when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. from any state, a transition to hardware standby mode occurs when stby is driven low. always select high-speed mode before making a transition to watch mode or sub-active mode. figure 22.1 mode transition diagram
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 555 of 656 rej09b0071-0500 table 22.2 low power dissipation mode transition conditions status of control bit at transition pre-transition state ssby pss lson dton state after transition invoked by sleep instruction state after transition back from low power mode invoked by interrupt 0 x 0 x sleep high-speed/medium-speed high-speed/ medium-speed 0 x 1 x ? ? 1 0 0 x software standby high-speed/medium-speed 1 0 1 x ? ? 1 1 0 0 watch high-speed 1 1 1 0 watch sub-active 1 1 0 1 ? ? 1 1 1 1 sub-active ? sub-active 0 0 x x ? ? 0 1 0 x ? ? 0 1 1 x sub-sleep sub-active 1 0 x x ? ? 1 1 0 0 watch high-speed 1 1 1 0 watch sub-active 1 1 0 1 high-speed ? 1 1 1 1 ? ? legend: x : don?t care ? : do not set.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 556 of 656 rej09b0071-0500 22.1 register description the following registers relates to the power-down modes. for details on system clock control register (sckcr), refer to section 21.1.1, system clock control register (sckcr). for details on low power control register (lpwrcr), refer to section 21.1.2, low power control register (lpwrcr). for details on timer control status regi ster (tcsr_1), refer to section 12.2.2, timer control/status register (tcsr). ? standby control register (sbycr) ? module stop control register a (mstpcra) ? module stop control register b (mstpcrb) ? module stop control register c (mstpcrc) ? module stop control register d (mstpcrd) ? low power control register (lpwrcr) ? system clock control register (sckcr) ? timer control status register (tcsr_1) 22.1.1 standby control register (sbycr) sbycr performs power-down mode control. bit bit name initial value r/w description 7 ssby 0 r/w software standby specifies transition destination when the sleep instruction is executed. 0: shifts to sleep mode when the sleep instruction is executed in high-speed mode or medium-speed mode. shifts to sub-sleep mode when the sleep instruction is executed in sub-active mode. 1: shifts to software standby mode, sub-active mode, and watch mode when the sleep instruction is executed in high-speed mode or medium-speed mode. shifts to watch mode or high-speed mode when the sleep instruction is executed in sub-active mode. note that the value of the ssby bit does not change even when software standby mode is canceled and making normal operation mode transition by executing an external interrupt. to clear this bit, 0 should be written to.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 557 of 656 rej09b0071-0500 bit bit name initial value r/w description 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits select the mcu wait time for clock settling to cancel software standby mode, watch mode, or sub- active mode. with a crystal resonator (table 22.3), select a wait time of 8 ms (oscillation settling time) or more, depending on the operating frequency. with an external clock, there are no specific wait requirements. 000: standby time = 8192 states 001: standby time = 16384 states 010: standby time = 32768 states 011: standby time = 65536 states 100: standby time = 131072 states 101: standby time = 262144 states 110: standby time = 2048 states 111: standby time = reserved 3 ? 1 r/w reserved this is a readable/writable bit, but the write value should always be 1. 2 to 0 ? all 0 ? reserved these bits are always read as 0 and cannot be modified.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 558 of 656 rej09b0071-0500 22.1.2 module stop control registers a to d (mstpcra to mstpcrd) mstpcr performs module stop mode control. when bits in mstpcr registers are set to 1, module stop mode is set. when cleared to 0, module stop mode is cleared. mstpcra bit bit name initial value r/w target module 7 mstpa7 * 1 0 r/w 6 mstpa6 * 2 0 r/w data transfer controller (dtc) 5 mstpa5 1 r/w 16-bit timer pulse unit (tpu) 4 mstpa4 1 r/w 8-bit timer (tmr_0, tmr_1) 3 mstpa3 * 1 1 r/w 2 mstpa2 * 1 1 r/w 1 mstpa1 1 r/w a/d converter 0 mstpa0 * 2 1 r/w 8-bit timer (tmr_2, tmr_3) mstpcrb bit bit name initial value r/w target module 7 mstpb7 1 r/w serial communication interface 0 (sci_0) 6 mstpb6 1 r/w serial communication interface 1 (sci_1) 5 mstpb5 * 1 1 r/w 4 mstpb4 1 r/w i 2 c bus interface 0 (i 2 c_0) (optional) 3 mstpb3 * 2 1 r/w i 2 c bus interface 1 (i 2 c_1) (optional) 2 mstpb2 * 1 1 r/w 1 mstpb1 * 1 1 r/w 0 mstpb0 * 1 1 r/w
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 559 of 656 rej09b0071-0500 mstpcrc bit bit name initial value r/w target module 7 mstpc7 1 r/w serial communication interface 2 (sci_2) 6 mstpc6 * 1 1 r/w 5 mstpc5 * 2 1 r/w d/a converter 4 mstpc4 * 2 1 r/w pc break controller (pbc) 3 mstpc3 * 1 1 r/w 2 mstpc2 * 2 1 r/w dtmf generation circuit 1 mstpc1 * 1 1 r/w 0 mstpc0 * 1 1 r/w mstpcrd bit bit name initial value r/w target module 7 mstpd7 * 1 1 r/w 6 mstpd6 1 r/w lcd controller/driver 5 mstpd5 * 2 1 r/w 8-bit reload timer (tmr_4) 4 mstpd4 * 1 1 r/w 3 mstpd3 * 1 1 r/w 2 mstpd2 * 1 1 r/w 1 mstpd1 * 1 1 r/w 0 mstpd0 * 1 1 r/w notes: 1. bit mstpa7 can be read/written to. this bit is initialized to 0. only 1 should be written to. bits mstpa3, mstpa2, mstpb5, ms tpb2 to mstpb0, mstpc6, mstpc3, mstpc1, mstpc0, mstpd7, mstpd4 to mstp d0 can be read/written to. these bits are initialized to 1. only 1 should be written to. 2. with the h8s/2264 group, only 1 should be written to.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 560 of 656 rej09b0071-0500 22.2 medium-speed mode in high-speed mode, when the sck2 to sck0 bits in sckcr are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck2 to sck0 bits. the bus masters other than the cpu (dtc * ) also operate in medium-speed mode. on-chip peripheral modules other than the bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and in ternal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is clear ed at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, and lson bit in lpwrcr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is executed with the ssby bit = 1, lson bit = 0, and pss bit in tcsr_1 (wdt_1) = 0, operation shifts to the software standby mode. when software standby mode is cleared by an external inte rrupt, medium-speed mode is restored. when the res pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 22.2 shows the timing for transition to and clearance of medium-speed mode. note: * supported only by the h8s/2268 group.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 561 of 656 rej09b0071-0500 internal clock , bus master clock peripheral module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 22.2 medium-speed mode transition and clearance timing 22.3 sleep mode 22.3.1 sleep mode when the sleep instruction is executed wh ile the sbycr ssby bit = 0 and the lpwrcr lson bit = 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops but the contents of the cpu?s internal registers are retained. other peripheral modules do not stop. 22.3.2 exiting sleep mode sleep mode is exited by any interrupt, or signals at the res , or stby pins. ? exiting sleep mode by interrupts when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. ? exiting sleep mode by res pin setting the res pin level low selects the reset state. after the stipulated reset input duration, driving the res pin high starts the cpu performing reset exception processing. ? exiting sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 562 of 656 rej09b0071-0500 22.4 software standby mode 22.4.1 software standby mode a transition is made to software standby mode when the sleep instruction is executed while the sbycr ssby bit = 1 and the lpwrcr lson bit = 0, and the tcsr_1 (wdt_1) pss bit = 0. in this mode, the cpu, on-chip peripheral modules, and oscillator all stop. however, the contents of the cpu?s internal registers, ram data, and the states of on-chip peripheral modules other than the a/d converter, and the states of i/o ports are retained. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 22.4.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 , irq1 , irq3 , irq4 , irq5 * , wkp0 to wkp7 ), or by means of the res pin or stby pin. ? clearing with an interrupt when an nmi, or irq0, irq1, irq3, irq4, irq5 * , or wkp0 to wkp7 interrupt request signal is input, clock oscillation starts, and after th e elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0, irq1, irq3, irq4, irq5 * , or wkp0 to wkp7 interrupt, set the corresponding enable b it/pin function switching bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0, irq1, irq3, irq4, irq5 * , or wkp0 to wkp7 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. ? clearing with the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire chip . note that the res pin must be held low until clock oscillation settles. when the res pin goes high, the cpu begins reset exception handling. ? clearing with the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. note: * supported only by the h8s/2268 group.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 563 of 656 rej09b0071-0500 22.4.3 oscillation settling time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. ? using a crystal oscillator set bits sts2 to sts0 so that the standby time is at l east 8 ms (the oscillation settling time). table 22.3 shows the standby times for differe nt operating frequencies and settings of bits sts2 to sts0. ? using an external clock any value can be set. normally, minimum time is recommended. note: the 16-state standby time cannot be used in the f-ztat versions; a standby time of 2048 states or longer should be used. table 22.3 oscillation settling time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 13 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.41 0.51 0.63 0.82 1.0 1.4 2.0 4.1 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 1.6 2.0 2.5 3.3 4.1 5.5 8.2 16.4 1 65536 states 3.3 4.1 5.0 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 6.6 8.2 10.1 13.1 16.4 21.8 32.8 65.5 1 262144 states 13.1 16.4 20.2 26.2 32.8 43.7 65.5 131.1 1 0 2048 states 0.10 0.13 0.16 0.20 0.26 0.34 0.51 1.0 1 16 states 0.8 1.0 1.2 1.6 2.0 2.7 4.0 8.0 s : recommended time setting 22.4.4 software standby mode application example figure 22.3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transiti on to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 564 of 656 rej09b0071-0500 oscillator internal clock nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation settling time t osc2 nmi exception handling figure 22.3 software standby mode application example 22.5 hardware standby mode 22.5.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter th e reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. do not change the state of the mode pins (md2, md1) during hardware standby mode. 22.5.2 clearing hardware standby mode hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator settles (at least t osc1 ms ? the oscillation settling time ? when using a crystal/ceramic oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 565 of 656 rej09b0071-0500 22.5.3 hardware standby mode timing figure 22.4 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation settling time, then changing the res pin from low to high. oscillator res stby oscillation settling time t osc1 reset exception handling figure 22.4 hardware standby mode timing 22.6 module stop mode module stop mode can be set for individual on-chip peripheral modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the a/d converter are retained. after reset clearance, all modules other than dtc * are in module stop mode. when an on-chip peripheral modul e is in module stop mode, read/write access to its registers is disabled. since the operations of the bus controller and i/o port are stopped when sleep mode is entered at the all-module stop state (mstpcr=h'ffffffff), power consumption can further be reduced. note: * supported only by the h8s/2268 group.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 566 of 656 rej09b0071-0500 22.7 watch mode 22.7.1 transition to watch mode cpu operation makes a transition to watch mode wh en the sleep instruction is executed in high- speed mode or sub-active mode with sbycr ssby=1, lpwrcr dton = 0, and tcsr_1 (wdt_1) pss = 1. in watch mode, the cpu is stopped and peripheral modules other than wdt_1, tmr_4 * , and lcd are also stopped. the contents of the cpu?s internal registers, the data in internal ram, and the statuses of the internal peripheral modules (excluding the a/d converter) and i/o ports are retained. to make a transition to watch mode, bits sck2 to sck0 in sckcr must be set to 0. note: * supported only by the h8s/2268 group. 22.7.2 exiting watch mode watch mode is exited by any interrupt (wovi1 interrupt, ovi4 to ovi7 interrupts * , nmi pin, or irq0 , irq1 , irq3 , irq4 , irq5 * , or wkp0 to wkp7 ), or signals at the res , or stby pins. ? exiting watch mode by interrupts when an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the lpwrcr lson bit = 0 or to sub-active mode when the lson bit = 1. when a transition is made to high-sp eed mode, a stable clock is supplied to all lsi circuits and interrupt exception processing starts after the time set in sbycr sts2 to sts0 has elapsed. in the case of irq0, irq1, irq3, irq4, irq5 * , and wkp0 to wkp7 interrupts, no transition is made from watch mode if the corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the internal peripheral modules, the interrupt enable register has been set to disabl e the reception of that interrupt, or is masked by the cpu. see section 22.4.3, oscillation settling time after clearing so ftware standby mode, for how to set the oscillation settling time when making a transition from watch mode to high-speed mode. ? exiting watch mode by res pins for exiting watch mode by the res pins, see section 22.4.2, clearing software standby mode. ? exiting watch mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. note: * supported only by the h8s/2268 group.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 567 of 656 rej09b0071-0500 22.8 sub-sleep mode 22.8.1 transition to sub-sleep mode when the sleep instruction is executed with the sbycr ssby bit = 0, lpwrcr lson bit = 1, and tcsr_1 (wdt_1) pss bit = 1, cpu operation shifts to sub-sleep mode. in sub-sleep mode, the cpu is stopped. peripheral modules other than tmr_0, tmr_1, tmr_2 to tmr_4 * , wdt_0, wdt_1, and lcd are also stopped. the contents of the cpu?s internal registers, the data in internal ram, and the statuses of the internal peripheral modules (excluding the a/d converter) and i/o ports are retained. note: * supported only by the h8s/2268 group. 22.8.2 exiting sub-sleep mode sub-sleep mode is exited by an interrupt (interrupts from internal peripheral modules, nmi pin, or irq0 , irq1 , irq3 , irq4 , irq5 * , or wkp0 to wkp7 ), or signals at the res or stby pins. ? exiting sub-sleep mode by interrupts when an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts. in the case of irq0 , irq1 , irq3 , irq4 , irq5 * , and wkp0 to wkp7 interrupts, sub-sleep mode is not cancelled if the corresponding en able bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the internal peripheral modules, the interrupt enable register has been set to disable the reception of that interr upt, or is masked by the cpu. ? exiting sub-sleep mode by res for exiting sub-sleep mode by the res pins, see section 22.4.2, clearing software standby mode. ? exiting sub-sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. note: * supported only by the h8s/2268 group.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 568 of 656 rej09b0071-0500 22.9 sub-active mode 22.9.1 transition to sub-active mode when the sleep instruction is executed in hi gh-speed mode with the sbycr ssby bit = 1, lpwrcr dton bit = 1, lson bit = 1, and tcsr_1 (wdt_1) pss bit = 1, cpu operation shifts to sub-active mode. when an interrupt occurs in watch mode, and if the lson bit of lpwrcr is 1, a transition is made to sub-active mode. and if an interrupt occurs in sub-sleep mode, a transition is made to sub-active mode. in sub-active mode, the cpu operates at low speed on the subclock, and the program is executed step by step. peripheral modules other than pbc * , tmr_0, tmr_1, tmr_2 to tmr_4 * , wdt_0, wdt_1, and lcd are also stopped. when operating the cpu in sub-active mode, the sc kcr sck2 to sck0 bits must be set to 0. note: * supported only by the h8s/2268 group. 22.9.2 exiting sub-active mode sub-active mode is exited by the sleep instruction or the res or stby pins. ? exiting sub-active mode by sleep instruction when the sleep instruction is executed with the sbycr ssby bit = 1, lpwrcr dton bit = 0, and tcsr_1 (wdt_1) pss bit = 1, the cpu exits sub-active mode and a transition is made to watch mode. when the sleep instructi on is executed with the sbycr ssby bit = 0, lpwrcr lson bit = 1, and tcsr (wdt_1) pss b it = 1, a transition is made to sub-sleep mode. finally, when the sleep instruction is executed with the sbycr ssby bit = 1, lpwrcr dton bit = 1, lson bit = 0, and tcsr (wdt_1) pss bit = 1, a direct transition is made to high-speed mode (sck0 to sck2 all 0). ? exiting sub-active mode by res pins for exiting sub-active mode by the res pins, see section 22.4.2, clearing software standby mode. ? exiting sub-active mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 569 of 656 rej09b0071-0500 22.10 direct transitions there are three modes, high-speed, medium-speed , and sub-active, in which the cpu executes programs. when a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. direct transitions are enabled by setting the lpwrcr dton bit to 1, then executing the sleep in struction. after a transition, direct transition interrupt exception processing starts. 22.10.1 direct transitions from high-speed mode to sub-active mode execute the sleep instruction in high-speed mode when the sbycr ssby bit = 1, lpwrcr lson bit = 1, and dton bit = 1, and tscr_1 (wdt_1) pss bit = 1 to make a transition to sub- active mode. 22.10.2 direct transition s from sub-active mode to high-speed mode execute the sleep instruction in sub-active mode when the sbycr ssby bit = 1, lpwrcr lson bit = 0, and dton bit = 1, and tscr_1 (wdt_1) pss bit = 1 to make a direct transition to high-speed mode after the time set in sbycr sts2 to sts0 has elapsed. 22.11 usage notes 22.11.1 i/o port status in software standby mode and watch mode, i/o por t states are retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.11.2 current dissipation during oscillation settling wait period current dissipation increases during the oscillation settling wait period. 22.11.3 dtc module stop (supported only by the h8s/2268 group) depending on the operating status of the dtc, the mstpa6 bit may not be set to 1. setting of the dtc module stop mode should be carried out only when the respective module is not activated. for details, refer to section 8, data transfer controller (dtc).
section 22 power-down modes rev. 5.00 sep. 01, 2009 page 570 of 656 rej09b0071-0500 22.11.4 on-chip peripheral module interrupt ? module stop mode relevant interrupt operations cannot be perf ormed in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc * activation source. interrupts should therefore be disabled before entering module stop mode. note: supported only by the h8s/2268 group. ? subactive mode / watch mode on-chip peripheral modules (dtc * , tpu, iic) that stop operation in subactive mode cannot clear interrupts in subactive mode. therefore, if subactive mode is entered when an interrupt is requested, cpu interrupt factors cannot be cleared. interrupts should therefore before executing the sleep instruction and entering subactive or watch mode. note: * supported only by the h8s/2268 group. 22.11.5 writing to mstpcr mstpcr should onl y be written to by the cpu. 22.11.6 entering subactive/watch mode and dtc module stop (supported only by h8s/2268 group) to enter subactive or watch mode, set dtc to module stop (write 1 to the mstpa6 bit) and reading the mstpa6 bit as 1 before transiting mode. after transiting from subactive mode to active mode, clear module stop. when dtc activation factor occu rs in subactive mode, dtc is activated when module stop is cleared after active mode is entered.
section 23 power supply circuit rev. 5.00 sep. 01, 2009 page 571 of 656 rej09b0071-0500 section 23 power supply circuit this lsi has an internal power step-down circuit bu ilt into it. using this circuit allows the internal power supply to be fixed at approximately 3.0 v without relaying on the power supply voltage connected to the external vcc terminal. this mean s that, when used at an external power supply higher than 3.0 v, the current consumption value can be suppressed to largely the same value as that when used at approximately 3.0 v. if the external voltage is 3.0 v or less, the internal voltage will be largely consistent with the external voltage. 23.1 when internal power st ep-down circuit is used as shown in figure 23.1, an external power supply should be connected to the vcc pin, using the shortest possible wiring, with a capacitance (h8s/2268 group: 0.1 f/0.2 f and h8s/2264 group: 0.2 f) between cvcc and vss. adding this external circuit makes the internal step-down circuit valid. applying a power supply exceeding th e absolute maximum rated value of 4.3 v to the cvcc terminal can permanently damage the lsi, so the power supply should not be connected to the cvcc terminal. the external power supply voltage connected to vcc and the gnd potential connected to vss serve as the references for the input/output levels of the external circuit. for example, a ?high? port input/output level will be the vcc refe rence, and a ?low? level will be the vss reference. the analog power supplies of the a/d converter, d/a converter * , and dtmf generation circuit * do not affect the internal step-down circuit. note: * supported only by the h8s/2268 group. vss cvcc vcc internal power supply internal logic vcc 2.7 to 5.5 v (vcc = 3.0 to 5.5 v for the f-ztat version) step-down voltage circuit stabilized capacitance (h8s/2268 group: 0.1 f/0.2 f and h8s/2264 group: 0.2 f) figure 23.1 power supply connections when internal power supply step-down circuit is used psckt20a_000020020700
section 23 power supply circuit rev. 5.00 sep. 01, 2009 page 572 of 656 rej09b0071-0500
section 24 list of registers rev. 5.00 sep. 01, 2009 page 573 of 656 rej09b0071-0500 section 24 list of registers this section gives information on the on-chip i/o registers and is configured as described below. 1. register addresses (by functional module, in address order) ? descriptions by functional module, in ascending order of addresses ? when registers consist of 16 bits, the addresses of the msbs are given. ? data bus width is given. ? the number of access states are given. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses (by functional module, in ascending order of addresses). ? reserved bits are indicated by ? in the bit name. ? when registers consist of 16 or 32 bits, bits are described from the msb side. 3. register states in each operating mode ? register states are described in the same order as the register addresses (by functional module, in ascending order of addresses). ? the register states described are for the basi c operating modes. if there is a specific reset for an on-chip module, refer to the section on that on-chip module.
section 24 list of registers rev. 5.00 sep. 01, 2009 page 574 of 656 rej09b0071-0500 24.1 register addresses (by function module, in address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the specified reference clock. register name abbreviation bit no. address * 1 module data width access state dtc mode register a * 4 mra 8 dtc 16/32 * 2 1 dtc source address register * 4 sar 24 h'ebc0 to h'efbf dtc 16/32 * 2 1 dtc mode register b * 4 mrb 8 dtc 16/32 * 2 1 dtc destination address register * 4 dar 24 dtc 16/32 * 2 1 dtc transfer count register a * 4 cra 16 dtc 16/32 * 2 1 dtc transfer count register b * 4 crb 16 dtc 16/32 * 2 1 lcd port control register lpcr 8 h'fc30 lcd 8/16 4 lcd control register lcr 8 h'fc31 lcd 8/16 4 lcd control register 2 lcr2 8 h'fc32 lcd 8/16 4 lcd ram ? 8 h'fc40 to h'fc53 lcd 8/16 4 module stop control register d mstpcrd 8 h'fc60 system 8 4 dtmf control register * 4 dtcr 8 h'fc68 dtmf 8 4 dtmf load register * 4 dtlr 8 h'fc69 dtmf 8 4 timer control register_4 * 4 tcr_4 8 h'fc70 tmr_4 8/16 4 timer control register_5 * 4 tcr_5 8 h'fc71 tmr_4 8/16 4 timer control register_6 * 4 tcr_6 8 h'fc72 tmr_4 8/16 4 timer control register_7 * 4 tcr_7 8 h'fc73 tmr_4 8/16 4 timer counter 4/timer reload register 4 * 4 tcnt_4(r)/ tlr_4(w) 8 h'fc74 tmr_4 8/16 4 timer counter 5/timer reload register 5 * 4 tcnt_5(r)/ tlr_5(w) 8 h'fc75 tmr_4 8/16 4 timer counter 6/timer reload register 6 * 4 tcnt_6(r)/ tlr_6(w) 8 h'fc76 tmr_4 8/16 4 timer counter 7/timer reload register 7 * 4 tcnt_7(r)/ tlr_7(w) 8 h'fc77 tmr_4 8/16 4
section 24 list of registers rev. 5.00 sep. 01, 2009 page 575 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state port h data direction register phddr 8 h'fc80 port 8 4 port j data direction register pjddr 8 h'fc81 port 8 4 port k data direction register pkddr 8 h'fc82 port 8 4 port l data direction register plddr 8 h'fc83 port 8 4 port m data direction register * 4 pmddr 8 h'fc84 port 8 4 port n data direction register * 4 pnddr 8 h'fc85 port 8 4 port h data register phdr 8 h'fc88 port 8 4 port j data register pjdr 8 h'fc89 port 8 4 port k data register pkdr 8 h'fc8a port 8 4 port l data register pldr 8 h'fc8b port 8 4 port m data register * 4 pmdr 8 h'fc8c port 8 4 port n data register * 4 pndr 8 h'fc8d port 8 4 port h register porth 8 h'fc90 port 8 4 port j register portj 8 h'fc91 port 8 4 port k register portk 8 h'fc92 port 8 4 port l register portl 8 h'fc93 port 8 4 port m register * 4 portm 8 h'fc94 port 8 4 port n register * 4 portn 8 h'fc95 port 8 4 port j pull-up mos control register pjpcr 8 h'fc99 port 8 4 wakeup control register wpcr 8 h'fc9f port 8 4 wakeup interrupt request register iwpr 8 h'fca0 int 8 4 interrupt enable register ienr1 8 h'fca1 int 8 4 d/a data register_0 * 4 dadr_0 8 h'fdac d/a 8 2 d/a data register_1 * 4 dadr_1 8 h'fdad d/a 8 2 d/a control register * 4 dacr 8 h'fdae d/a 8 2 serial control register x scrx 8 h'fdb4 iic, flash 8 2 ddc switch register ddcswr 8 h'fdb5 iic 8 2 timer control register_2 * 4 tcr_2 8 h'fdc0 tmr_2 8 2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 576 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state timer control register_3 * 4 tcr_3 8 h'fdc1 tmr_3 8 2 timer control/status register_2 * 4 tcsr_2 8 h'fdc2 tmr_2 8 2 timer control/status register_3 * 4 tcsr_3 8 h'fdc3 tmr_3 8 2 time constant register a_2 * 4 tcora_2 8 h'fdc4 tmr_2 8/16 2 time constant register a_3 * 4 tcora_3 8 h'fdc5 tmr_3 8/16 2 time constant register b_2 * 4 tcorb_2 8 h'fdc6 tmr_2 8/16 2 time constant register b_3 * 4 tcorb_3 8 h'fdc7 tmr_3 8/16 2 timer counter_2 * 4 tcnt_2 8 h'fdc8 tmr_2 8/16 2 timer counter_3 * 4 tcnt_3 8 h'fdc9 tmr_3 8/16 2 serial mode register_2 smr_2 8 h'fdd0 sci_2 8 2 bit rate register_2 brr_2 8 h'fdd1 sci_2 8 2 serial control register_2 scr_2 8 h'fdd2 sci_2 8 2 transmit data register_2 tdr_2 8 h'fdd3 sci_2 8 2 serial status register_2 ssr_2 8 h'fdd4 sci_2 8 2 receive data register_2 rdr_2 8 h'fdd5 sci_2 8 2 smart card mode register_2 scmr_2 8 h'fdd6 sci_2 8 2 standby control register sbycr 8 h'fde4 system 8 2 system control register syscr 8 h'fde5 system 8 2 system clock control register sckcr 8 h'fde6 system 8 2 mode control register mdcr 8 h'fde7 system 8 2 module stop control register a mstpcra 8 h'fde8 system 8 2 module stop control register b mstpcrb 8 h'fde9 system 8 2 module stop control register c mstpcrc 8 h'fdea system 8 2 low power control register lpwrcr 8 h'fdec system 8 2 serial expansion mode register_0 semr_0 8 h'fdf8 sci_0 8 2 break address register a * 4 bara 32 h'fe00 pbc 8/16 2 break address register b * 4 barb 32 h'fe04 pbc 8/16 2 break control register a * 4 bcra 8 h'fe08 pbc 8/16 2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 577 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state break control register b * 4 bcrb 8 h'fe09 pbc 8/16 2 irq sense control register h iscrh 8 h'fe12 int 8 2 irq sense control register l iscrl 8 h'fe13 int 8 2 irq enable register ier 8 h'fe14 int 8 2 irq status register isr 8 h'fe15 int 8 2 dtc enable register * 4 dtcer 8 h'fe16 to h'fe1b, h'fe1e dtc 8 2 dtc vector register * 4 dtvecr 8 h'fe1f dtc 8 2 port 1 data direction register p1ddr 8 h'fe30 port 8 2 port 3 data direction register p3ddr 8 h'fe32 port 8 2 port 7 data direction register p7ddr 8 h'fe36 port 8 2 port f data direction register pfddr 8 h'fe3e port 8 2 port 3 open drain control register p3odr 8 h'fe46 port 8 2 timer start register tstr 8 h'feb0 tpu 8 2 timer synchro register tsyr 8 h'feb1 tpu 8 2 interrupt priority register a * 4 ipra 8 h'fec0 int 8 2 interrupt priority register b * 4 iprb 8 h'fec1 int 8 2 interrupt priority register c * 4 iprc 8 h'fec2 int 8 2 interrupt priority register d * 4 iprd 8 h'fec3 int 8 2 interrupt priority register e * 4 ipre 8 h'fec4 int 8 2 interrupt priority register f * 4 iprf 8 h'fec5 int 8 2 interrupt priority register g * 4 iprg 8 h'fec6 int 8 2 interrupt priority register i * 4 ipri 8 h'fec8 int 8 2 interrupt priority register j * 4 iprj 8 h'fec9 int 8 2 interrupt priority register k * 4 iprk 8 h'feca int 8 2 interrupt priority register l * 4 iprl 8 h'fecb int 8 2 interrupt priority register m * 4 iprm 8 h'fecc int 8 2 interrupt priority register o * 4 ipro 8 h'fece int 8 2 ram emulation register * 4 ramer 8 h'fedb flash 8 2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 578 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state port 1 data register p1dr 8 h'ff00 port 8 2 port 3 data register p3dr 8 h'ff02 port 8 2 port 7 data register p7dr 8 h'ff06 port 8 2 port f data register pfdr 8 h'ff0e port 8 2 timer control register_0 * 4 tcr_0 8 h'ff10 tpu_0 8 2 timer mode register_0 * 4 tmdr_0 8 h'ff11 tpu_0 8 2 timer i/o control register h_0 * 4 tiorh_0 8 h'ff12 tpu_0 8 2 timer i/o control register l_0 * 4 tiorl_0 8 h'ff13 tpu_0 8 2 timer interrupt enable register_0 * 4 tier_0 8 h'ff14 tpu_0 8 2 timer status register_0 * 4 tsr_0 8 h'ff15 tpu_0 8 2 timer counter_0 * 4 tcnt_0 16 h'ff16 tpu_0 16 2 timer general register a_0 * 4 tgra_0 16 h'ff18 tpu_0 16 2 timer general register b_0 * 4 tgrb_0 16 h'ff1a tpu_0 16 2 timer general register c_0 * 4 tgrc_0 16 h'ff1c tpu_0 16 2 timer general register d_0 * 4 tgrd_0 16 h'ff1e tpu_0 16 2 timer control register_1 tcr_1 8 h'ff20 tpu_1 8 2 timer mode register_1 tmdr_1 8 h'ff21 tpu_1 8 2 timer i/o control register_1 tior_1 8 h'ff22 tpu_1 8 2 timer interrupt enable register_1 tier_1 8 h'ff24 tpu_1 8 2 timer status register_1 tsr_1 8 h'ff25 tpu_1 8 2 timer counter_1 tcnt_1 16 h'ff26 tpu_1 16 2 timer general register a_1 tgra_1 16 h'ff28 tpu_1 16 2 timer general register b_1 tgrb_1 16 h'ff2a tpu_1 16 2 timer control register_2 tcr_2 8 h'ff30 tpu_2 8 2 timer mode register_2 tmdr_2 8 h'ff31 tpu_2 8 2 timer i/o control register_2 tior_2 8 h'ff32 tpu_2 8 2 timer interrupt enable register_2 tier_2 8 h'ff34 tpu_2 8 2 timer status register_2 tsr_2 8 h'ff35 tpu_2 8 2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 579 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state timer counter_2 tcnt_2 16 h'ff36 tpu_2 16 2 timer general register a_2 tgra_2 16 h'ff38 tpu_2 16 2 timer general register b_2 tgrb_2 16 h'ff3a tpu_2 16 2 timer control register_0 tcr_0 8 h'ff68 tmr_0 8 2 timer control register_1 tcr_1 8 h'ff69 tmr_1 8 2 timer control/status register_0 tcsr_0 8 h'ff6a tmr_0 8 2 timer control/status register_1 tcsr_1 8 h'ff6b tmr_1 8 2 time constant register a_0 tcora_0 8 h'ff6c tmr_0 8/16 2 time constant register a_1 tcora_1 8 h'ff6d tmr_1 8/16 2 time constant register b_0 tcorb_0 8 h'ff6e tmr_0 8/16 2 time constant register b_1 tcorb_1 8 h'ff6f tmr_1 8/16 2 timer counter_0 tcnt_0 8 h'ff70 tmr_0 8/16 2 timer counter_1 tcnt_1 8 h'ff71 tmr_1 8/16 2 timer control/status register_0 tcsr_0 8 h'ff74(w) h'ff74(r) wdt_0 16 2 timer counter_0 tcnt_0 8 h'ff74(w) h'ff75(r) wdt_0 16 2 reset control/status register rstcsr 8 h'ff76(w) h'ff77(r) wdt_0 16 2 serial mode register_0 smr_0 8 h'ff78 * 3 sci_0 8 2 i 2 c bus control register_0 iccr_0 8 h'ff78 * 3 iic_0 8 2 bit rate register_0 brr_0 8 h'ff79 * 3 sci_0 8 2 i 2 c bus status register_0 icsr_0 8 h'ff79 * 3 iic_0 8 2 serial control register_0 scr_0 8 h'ff7a sci_0 8 2 transmit data register_0 tdr_0 8 h'ff7b sci_0 8 2 serial status register_0 ssr_0 8 h'ff7c sci_0 8 2 receive data register_0 rdr_0 8 h'ff7d sci_0 8 2 smart card mode register_0 scmr_0 8 h'ff7e * 3 sci_0 8 2 i 2 c bus data register_0/second slave address register_0 icdr_0/ sarx_0 8 h'ff7e * 3 iic_0 8 2 i 2 c bus mode register_0/slave address register_0 icmr_0/ sar_0 8 h'ff7f iic_0 8 2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 580 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state serial mode register_1 smr_1 8 h'ff80 * 3 sci_1 8 2 i 2 c bus control register_1 * 4 iccr_1 8 h'ff80 * 3 iic_1 8 2 bit rate register_1 brr_1 8 h'ff81 * 3 sci_1 8 2 i 2 c bus status register_1 * 4 icsr_1 8 h'ff81 * 3 iic_1 8 2 serial control register_1 scr_1 8 h'ff82 sci_1 8 2 transmit data register_1 tdr_1 8 h'ff83 sci_1 8 2 serial status register_1 ssr_1 8 h'ff84 sci_1 8 2 receive data register_1 rdr_1 8 h'ff85 sci_1 8 2 smart card mode register_1 scmr_1 8 h'ff86 * 3 sci_1 8 2 i 2 c bus data register_1/second slave address register_1 * 4 icdr_1/ sarx_1 8 h'ff86 * 3 iic_1 8 2 i 2 c bus mode register_1/slave address register_1 * 4 icmr_1/ sar_1 8 h'ff87 iic_1 8 2 a/d data register ah addrah 8 h'ff90 a/d 8 2 a/d data register al addral 8 h'ff91 a/d 8 2 a/d data register bh addrbh 8 h'ff92 a/d 8 2 a/d data register bl addrbl 8 h'ff93 a/d 8 2 a/d data register ch addrch 8 h'ff94 a/d 8 2 a/d data register cl addrcl 8 h'ff95 a/d 8 2 a/d data register dh addrdh 8 h'ff96 a/d 8 2 a/d data register dl addrdl 8 h'ff97 a/d 8 2 a/d control/status register adcsr 8 h'ff98 a/d 8 2 a/d control register adcr 8 h'ff99 a/d 8 2 timer control/status register_1 tcsr_1 8 h'ffa2(w) h'ffa2(r) wdt_1 16 2 timer counter_1 tcnt_1 8 h'ffa2(w) h'ffa3(r) wdt_1 16 2 flash memory control register 1 * 4 flmcr1 8 h'ffa8 flash 8 2 flash memory control register 2 * 4 flmcr2 8 h'ffa9 flash 8 2 erase block register 1 * 4 ebr1 8 h'ffaa flash 8 2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 581 of 656 rej09b0071-0500 register name abbreviation bit no. address * 1 module data width access state erase block register 2 * 4 ebr2 8 h'ffab flash 8 2 flash memory power control register * 4 flpwcr 8 h'ffac flash 8 2 port 1 register port1 8 h'ffb0 port 8 2 port 3 register port3 8 h'ffb2 port 8 2 port 4 register port4 8 h'ffb3 port 8 2 port 7 register port7 8 h'ffb6 port 8 2 port 9 register port9 8 h'ffb8 port 8 2 port f register portf 8 h'ffbe port 8 2 notes: 1. lower 16 bits of the address. 2. allocated on the on-chip ram. 32-bit bus wh en dtc accesses as register information, and 16-bit in other cases. 3. part of registers sci_0 and sci_1 and part of registers iic_0 and iic_1 * 4 are allocated to the same address. use the iice bit of the serial control register x (scrx) to select the register. 4. supported only by the h8s/2268 group.
section 24 list of registers rev. 5.00 sep. 01, 2009 page 582 of 656 rej09b0071-0500 24.2 register bits register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mra * 1 sm1 sm0 dm1 dm0 md1 md0 dts sz dtc sar * 1 mrb * 1 chne disel ? ? ? ? ? ? dar * 1 cra * 1 crb * 1 lpcr dts1 dts0 cmx ? sgs3 sgs2 sgs1 sgs0 lcd lcr ? psw act disp cks3 cks2 cks1 cks0 lcr2 lcdab ? hcks * 2 sups * 2 cds3 cds2 cds1 cds0 lcd ram bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mstpcrd mstpd7 mstpd6 mstpd5 mstpd4 mstpd3 mstpd2 mstpd1 mstpd0 system dtcr * 1 dten ? cloe rwoe clf1 clf0 rwf1 rwf0 dtmf dtlr * 1 ? ? dtl5 dtl4 dtl3 dtl2 dtl1 dtl0 tcr_4 * 1 arsl ovf ovie ? ? cks2 cks1 cks0 tmr_4 tcr_5 * 1 arsl ovf ovie ? ? cks2 cks1 cks0 tcr_6 * 1 arsl ovf ovie ? ? cks2 cks1 cks0 tcr_7 * 1 arsl ovf ovie ? ? cks2 cks1 cks0 tcnt_4(r)/ tlr_4(w) * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcnt_5(r)/ tlr_5(w) * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcnt_6(r)/ tlr_6(w) * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcnt_7(r)/ tlr_7(w) * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
section 24 list of registers rev. 5.00 sep. 01, 2009 page 583 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module phddr ? ? ? ? ph3ddr ph2ddr ph1ddr ph0ddr port pjddr pj7ddr pj6ddr pj5ddr pj4ddr pj3ddr pj2ddr pj1ddr pj0ddr pkddr pk7ddr pk6ddr pk5ddr pk4ddr pk3ddr pk2ddr pk1ddr pk0ddr plddr pl7ddr pl6ddr pl5ddr pl4ddr pl3ddr pl2ddr pl1ddr pl0ddr pmddr * 1 pm7ddr pm6ddr pm5ddr pm4ddr pm3ddr pm2ddr pm1ddr pm0ddr pnddr * 1 pn7ddr pn6ddr pn5ddr pn4ddr pn3ddr pn2ddr pn1ddr pn0ddr phdr ? ? ? ? ph3dr ph2dr ph1dr ph0dr pjdr pj7dr pj6dr pj5dr pj4dr pj3dr pj2dr pj1dr pj0dr pkdr pk7dr pk6dr pk5dr pk4dr pk3dr pk2dr pk1dr pk0dr pldr pl7dr pl6dr pl5dr pl4dr pl3dr pl2dr pl1dr pl0dr pmdr * 1 pm7dr pm6dr pm5dr pm4dr pm3dr pm2dr pm1dr pm0dr pndr * 1 pn7dr pn6dr pn5dr pn4dr pn3dr pn2dr pn1dr pn0dr porth ph7 ? ? ? ph3 ph2 ph1 ph0 portj pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 portk pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 portl pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 portm * 1 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 portn * 1 pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 pjpcr pj7pcr pj6pcr pj5pcr pj4p cr pj3pcr pj2pcr pj1pcr pj0pcr wpcr wpc7 wpc6 wpc5 wpc4 wpc3 wpc2 wpc1 wpc0 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 int ienr1 ienwp ? ? ? ? ? ? ? dadr_0 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d/a dadr_1 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dacr * 1 daoe1 daoe0 dae ? ? ? ? ? scrx ? iicx1 * 2 iicx0 iice flshe * 1 ? ? ? iic, flash ddcswr ? ? ? ? clr3 clr2 clr1 clr0 iic tcr_2 * 1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_2 tcr_3 * 1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_3 tcsr_2 * 1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_2
section 24 list of registers rev. 5.00 sep. 01, 2009 page 584 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcsr_3 * 1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_3 tcora_2 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_2 tcora_3 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_3 tcorb_2 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_2 tcorb_3 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_3 tcnt_2 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_2 tcnt_3 * 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_3 smr_2 c/ a chr pe o/ e stop mp cks1 cks0 sci_2 smr_2 gm blk pe o/ e bcp1 bcp0 cks1 cks0 brr_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scr_2 tie rie te re mpie teie cke1 cke0 tdr_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr_2 tdre rdrf orer fer per tend mpb mpbt ssr_2 tdre rdrf orer ers per tend mpb mpbt rdr_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scmr_2 ? ? ? ? sdir sinv ? smif sbycr ssby sts2 sts1 sts0 ? ? ? ? system syscr ? ? intm1 intm0 nmieg ? ? ? sckcr ? ? ? ? ? sck2 sck1 sck0 mdcr ? ? ? ? ? mds2 mds1 ? mstpcra mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 mstpcrb mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 lpwrcr dton lson nesel substp rfcut ? stc1 stc0 semr0 ? ? ? ? abcs acs2 acs1 acs0 sci_0 bara * 1 ? ? ? ? ? ? ? ? pbc baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0
section 24 list of registers rev. 5.00 sep. 01, 2009 page 585 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module barb * 1 ? ? ? ? ? ? ? ? pbc bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bcra * 1 cmfa cda bamra2 bamra1 bamra0 csela1 csela0 biea bcrb * 1 cmfb cdb bamrb2 bamrb1 bamrb0 cselb1 cselb0 bieb iscrh ? ? ? ? irq5scb * 2 irq5sca * 2 irq4scb irq4sca int iscrl irq3scb irq3sca ? ? irq1 scb irq1sca irq0scb irq0sca ier ? ? irq5e * 2 irq4e irq3e ? irq1e irq0e isr ? ? irq5f * 2 irq4f irq3f ? irq1f irq0f dtcer * 1 dtce7 dtce6 dtce5 dtce4 dt ce3 dtce2 dtce1 dtce0 dtc dtvecr * 1 swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 p1ddr p17ddr p16ddr p15ddr p14ddr p 13ddr p12ddr p11ddr p10ddr port p3ddr ? ? p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr p7ddr p77ddr p76ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr pfddr ? ? ? ? pf3ddr ? ? ? p3odr ? ? p35odr p34odr p33odr p32odr p31odr p30odr tstr ? ? ? ? ? cst2 cst1 cst0 * 2 tpu tsyr ? ? ? ? ? sync2 sync1 sync0 * 2 ipra * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 int iprb * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprc * 1 ? ? ? ? ? ipr2 ipr1 ipr0 iprd * 1 ? ipr6 ipr5 ipr4 ? ? ? ? ipre * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprf * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprg * 1 ? ipr6 ipr5 ipr4 ? ? ? ? ipri * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprj * 1 ? ? ? ? ? ipr2 ipr1 ipr0 iprk * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprl * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0
section 24 list of registers rev. 5.00 sep. 01, 2009 page 586 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module iprm * 1 ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 int ipro * 1 ? ipr6 ipr5 ipr4 ? ? ? ? ramer * 1 ? ? ? ? rams ram2 ram1 ram0 flash p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr port p3dr ? ? p35dr p34dr p33dr p32dr p31dr p30dr p7dr p77dr p76dr p75dr p74dr p73dr p72dr p71dr p70dr pfdr ? ? ? ? pf3dr ? ? ? tcr_0 * 1 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_0 tmdr_0 * 1 ? ? bfb bfa md3 md2 md1 md0 tiorh_0 * 1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 * 1 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_0 * 1 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 * 1 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 * 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgra_0 * 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_0 * 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrc_0 * 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrd_0 * 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcr_1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_1 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu * 2 tciev ? ? tgieb tgiea tsr_1 tcfd * 2 ? tcfu * 2 tcfv ? ? tgfb tgfa tcnt_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
section 24 list of registers rev. 5.00 sep. 01, 2009 page 587 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tgra_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 tpu_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcr_2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_2 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu * 2 tciev ? ? tgieb tgiea tsr_2 tcfd * 2 ? tcfu * 2 tcfv ? ? tgfb tgfa tcnt_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgra_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcr_0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_0 tcr_1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_1 tcsr_0 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_0 tcsr_1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_1 tcora_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_0 tcora_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_1 tcorb_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_0 tcorb_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_1 tcnt_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_0 tcnt_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_1 tcsr_0 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt_0 tcnt_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rstcsr wovf rste ? ? ? ? ? ? smr_0 c/ a chr pe o/ e stop mp cks1 cks0 sci_0 smr_0 gm blk pe o/ e bcp1 bcp0 cks1 cks0
section 24 list of registers rev. 5.00 sep. 01, 2009 page 588 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module iccr_0 ice ieic mst trs acke bbsy iric scp iic_0 brr_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sci_0 icsr_0 estp stop irtr aasx al aas adz ackb iic_0 scr_0 tie rie te re mpie teie cke1 cke0 sci_0 tdr_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr_0 tdre rdrf orer fer per tend mpb mpbt ssr_0 tdre rdrf orer ers per tend mpb mpbt rdr_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scmr_0 ? ? ? ? sdir sinv ? smif icdr_0/ sarx_0 icdr7/ svax6 icdr6/ svax5 icdr5/ svax4 icdr4/ svax3 icdr3/ svax2 icdr2/ svax1 icdr1/ svax0 icdr0/ fsx iic_0 icmr_0/ sar_0 mls/ sva6 wait/ sva5 cks2/ sva4 cks1/ sva3 cks0/ sva2 bc2/ sva1 bc1/ sva0 bc0/ fs smr_1 c/ a chr pe o/ e stop mp cks1 cks0 sci_1 smr_1 gm blk pe o/ e bcp1 bcp0 cks1 cks0 iccr_1 * 1 ice ieic mst trs acke bbsy iric scp iic_1 brr_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sci_1 icsr_1 * 1 estp stop irtr aasx al aas adz ackb iic_1 scr_1 tie rie te re mpie teie cke1 cke0 sci_1 tdr_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr_1 tdre rdrf orer fer per tend mpb mpbt ssr_1 tdre rdrf orer ers per tend mpb mpbt rdr_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scmr_1 ? ? ? ? sdir sinv ? smif icdr_1/ sarx_1 * 1 icdr7/ svax6 icdr6/ svax5 icdr5/ svax4 icdr4/ svax3 icdr3/ svax2 icdr2/ svax1 icdr1/ svax0 icdr0/fsx iic_1 icmr_1/ sar_1 * 1 mls/ sva6 wait/ sva5 cks2/ sva4 cks1/ sva3 cks0/ sva2 bc2/ sva1 bc1/ sva0 bc0/fs addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d addral ad1 ad0 ? ? ? ? ? ? addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrbl ad1 ad0 ? ? ? ? ? ?
section 24 list of registers rev. 5.00 sep. 01, 2009 page 589 of 656 rej09b0071-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d addrcl ad1 ad0 ? ? ? ? ? ? addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrdl ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst scan ch3 ch2 ch1 ch0 adcr trgs1 trgs0 ? ? cks1 cks0 ? ? tcsr_1 ovf wt/ it tme pss rst/ nmi cks2 cks1 cks0 wdt_1 tcnt_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 flmcr1 * 1 fwe swe1 esu1 psu1 ev1 pv1 e1 p1 flash flmcr2 * 1 fler ? ? ? ? ? ? ? ebr1 * 1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ebr2 * 1 ? ? ? ? eb11 eb10 eb9 eb8 flpwcr * 1 pdwnd ? ? ? ? ? ? ? port1 p17 p16 p15 p14 p13 p12 p11 p10 port port3 ? ? p35 p34 p33 p32 p31 p30 port4 p47 p46 p45 p44 p43 p42 p41 p40 port7 p77 p76 p75 p74 p73 p72 p71 p70 port9 p97 p96 ? ? ? ? ? ? portf ? ? ? ? pf3 ? ? ? notes: 1. supported only by the h8s/2268 group. 2. reserved in the h8s/2264 group.
section 24 list of registers rev. 5.00 sep. 01, 2009 page 590 of 656 rej09b0071-0500 24.3 register states in each operating mode register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module mra * ? ? ? ? ? ? ? ? ? ? dtc sar * ? ? ? ? ? ? ? ? ? ? mrb * ? ? ? ? ? ? ? ? ? ? dar * ? ? ? ? ? ? ? ? ? ? cra * ? ? ? ? ? ? ? ? ? ? crb * ? ? ? ? ? ? ? ? ? ? lpcr initialized ? ? ? ? ? ? ? ? initialized lcd lcr initialized ? ? ? ? ? ? ? ? initialized lcr2 initialized ? ? ? ? ? ? ? ? initialized lcd ram ? ? ? ? ? ? ? ? ? ? mstpcrd initialized ? ? ? ? ? ? ? ? initialized system dtcr * initialized ? ? ? ? ? ? ? ? initialized dtmf dtlr * initialized ? ? ? ? ? ? ? ? initialized tcr_4 * initialized ? ? ? ? ? ? ? ? initialized tmr_4 tcr_5 * initialized ? ? ? ? ? ? ? ? initialized tcr_6 * initialized ? ? ? ? ? ? ? ? initialized tcr_7 * initialized ? ? ? ? ? ? ? ? initialized tcnt_4/ tlr_4 * initialized ? ? ? ? ? ? ? ? initialized tcnt_5/ tlr_5 * initialized ? ? ? ? ? ? ? ? initialized tcnt_6/ tlr_6 * initialized ? ? ? ? ? ? ? ? initialized tcnt_7/ tlr_7 * initialized ? ? ? ? ? ? ? ? initialized phddr initialized ? ? ? ? ? ? ? ? initialized port pjddr initialized ? ? ? ? ? ? ? ? initialized pkddr initialized ? ? ? ? ? ? ? ? initialized plddr initialized ? ? ? ? ? ? ? ? initialized pmddr * initialized ? ? ? ? ? ? ? ? initialized
section 24 list of registers rev. 5.00 sep. 01, 2009 page 591 of 656 rej09b0071-0500 register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module pnddr * initialized ? ? ? ? ? ? ? ? initialized port phdr initialized ? ? ? ? ? ? ? ? initialized pjdr initialized ? ? ? ? ? ? ? ? initialized pkdr initialized ? ? ? ? ? ? ? ? initialized pldr initialized ? ? ? ? ? ? ? ? initialized pmdr * initialized ? ? ? ? ? ? ? ? initialized pndr * initialized ? ? ? ? ? ? ? ? initialized porth initialized ? ? ? ? ? ? ? ? initialized portj initialized ? ? ? ? ? ? ? ? initialized portk initialized ? ? ? ? ? ? ? ? initialized portl initialized ? ? ? ? ? ? ? ? initialized portm * initialized ? ? ? ? ? ? ? ? initialized portn * initialized ? ? ? ? ? ? ? ? initialized pjpcr initialized ? ? ? ? ? ? ? ? initialized wpcr initialized ? ? ? ? ? ? ? ? initialized iwpr initialized ? ? ? ? ? ? ? ? initialized int ienr1 initialized ? ? ? ? ? ? ? ? initialized dadr_0 * initialized ? ? ? ? ? ? ? ? initialized d/a dadr_1 * initialized ? ? ? ? ? ? ? ? initialized dacr initialized ? ? ? ? ? ? ? ? initialized scrx initialized ? ? ? ? ? ? ? ? initialized iic, flash ddcswr initialized ? ? ? ? ? ? ? ? initialized iic tcr_2 * initialized ? ? ? ? ? ? ? ? initialized tmr_2 tcr_3 * initialized ? ? ? ? ? ? ? ? initialized tmr_3 tcsr_2 * initialized ? ? ? ? ? ? ? ? initialized tmr_2 tcsr_3 * initialized ? ? ? ? ? ? ? ? initialized tmr_3 tcora_2 * initialized ? ? ? ? ? ? ? ? initialized tmr_2 tcora_3 * initialized ? ? ? ? ? ? ? ? initialized tmr_3 tcorb_2 * initialized ? ? ? ? ? ? ? ? initialized tmr_2 tcorb_3 * initialized ? ? ? ? ? ? ? ? initialized tmr_3
section 24 list of registers rev. 5.00 sep. 01, 2009 page 592 of 656 rej09b0071-0500 register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module tcnt_2 * initialized ? ? ? ? ? ? ? ? initialized tmr_2 tcnt_3 * initialized ? ? ? ? ? ? ? ? initialized tmr_3 smr_2 initialized ? ? ? ? ? ? ? ? initialized sci_2 brr_2 initialized ? ? ? ? ? ? ? ? initialized scr_2 initialized ? ? ? ? ? ? ? ? initialized tdr_2 initialized ? ? ? initialized initialized initialized initialized initialized initialized ssr_2 initialized ? ? ? initialized initialized in itialized initialized initialized initialized rdr_2 initialized ? ? ? initialized initialized initialized initialized initialized initialized scmr_2 initialized ? ? ? ? ? ? ? ? initialized sbycr initialized ? ? ? ? ? ? ? ? initialized system syscr initialized ? ? ? ? ? ? ? ? initialized sckcr initialized ? ? ? ? ? ? ? ? initialized mdcr initialized ? ? ? ? ? ? ? ? initialized mstpcra initialized ? ? ? ? ? ? ? ? initialized mstpcrb initialized ? ? ? ? ? ? ? ? initialized mstpcrc initialized ? ? ? ? ? ? ? ? initialized lpwrcr initialized ? ? ? ? ? ? ? ? initialized semr_0 initialized ? ? ? ? ? ? ? ? initialized sci_0 bara * initialized ? ? ? ? ? ? ? ? initialized pbc barb * initialized ? ? ? ? ? ? ? ? initialized bcra * initialized ? ? ? ? ? ? ? ? initialized bcrb * initialized ? ? ? ? ? ? ? ? initialized iscrh initialized ? ? ? ? ? ? ? ? initialized int iscrl initialized ? ? ? ? ? ? ? ? initialized ier initialized ? ? ? ? ? ? ? ? initialized isr initialized ? ? ? ? ? ? ? ? initialized dtcer * initialized ? ? ? ? ? ? ? ? initialized dtc dtvecr * initialized ? ? ? ? ? ? ? ? initialized p1ddr initialized ? ? ? ? ? ? ? ? initialized port p3ddr initialized ? ? ? ? ? ? ? ? initialized p7ddr initialized ? ? ? ? ? ? ? ? initialized
section 24 list of registers rev. 5.00 sep. 01, 2009 page 593 of 656 rej09b0071-0500 register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module pfddr initialized ? ? ? ? ? ? ? ? initialized port p3odr initialized ? ? ? ? ? ? ? ? initialized tstr initialized ? ? ? ? ? ? ? ? initialized tpu tsyr initialized ? ? ? ? ? ? ? ? initialized ipra * initialized ? ? ? ? ? ? ? ? initialized int iprb * initialized ? ? ? ? ? ? ? ? initialized iprc * initialized ? ? ? ? ? ? ? ? initialized iprd * initialized ? ? ? ? ? ? ? ? initialized ipre * initialized ? ? ? ? ? ? ? ? initialized iprf * initialized ? ? ? ? ? ? ? ? initialized iprg * initialized ? ? ? ? ? ? ? ? initialized ipri * initialized ? ? ? ? ? ? ? ? initialized iprj * initialized ? ? ? ? ? ? ? ? initialized iprk * initialized ? ? ? ? ? ? ? ? initialized iprl * initialized ? ? ? ? ? ? ? ? initialized iprm * initialized ? ? ? ? ? ? ? ? initialized ipro * initialized ? ? ? ? ? ? ? ? initialized ramer * initialized ? ? ? ? ? ? ? ? initialized flash p1dr initialized ? ? ? ? ? ? ? ? initialized port p3dr initialized ? ? ? ? ? ? ? ? initialized p7dr initialized ? ? ? ? ? ? ? ? initialized pfdr initialized ? ? ? ? ? ? ? ? initialized tcr_0 * initialized ? ? ? ? ? ? ? ? initialized tpu_0 tmdr_0 * initialized ? ? ? ? ? ? ? ? initialized tiorh_0 * initialized ? ? ? ? ? ? ? ? initialized tiorl_0 * initialized ? ? ? ? ? ? ? ? initialized tier_0 * initialized ? ? ? ? ? ? ? ? initialized tsr_0 * initialized ? ? ? ? ? ? ? ? initialized tcnt_0 * initialized ? ? ? ? ? ? ? ? initialized tgra_0 * initialized ? ? ? ? ? ? ? ? initialized tgrb_0 * initialized ? ? ? ? ? ? ? ? initialized
section 24 list of registers rev. 5.00 sep. 01, 2009 page 594 of 656 rej09b0071-0500 register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module tgrc_0 * initialized ? ? ? ? ? ? ? ? initialized tpu_0 tgrd_0 * initialized ? ? ? ? ? ? ? ? initialized tcr_1 initialized ? ? ? ? ? ? ? ? initialized tpu_1 tmdr_1 initialized ? ? ? ? ? ? ? ? initialized tior_1 initialized ? ? ? ? ? ? ? ? initialized tier_1 initialized ? ? ? ? ? ? ? ? initialized tsr_1 initialized ? ? ? ? ? ? ? ? initialized tcnt_1 initialized ? ? ? ? ? ? ? ? initialized tgra_1 initialized ? ? ? ? ? ? ? ? initialized tgrb_1 initialized ? ? ? ? ? ? ? ? initialized tcr_2 initialized ? ? ? ? ? ? ? ? initialized tpu_2 tmdr_2 initialized ? ? ? ? ? ? ? ? initialized tior_2 initialized ? ? ? ? ? ? ? ? initialized tier_2 initialized ? ? ? ? ? ? ? ? initialized tsr_2 initialized ? ? ? ? ? ? ? ? initialized tcnt_2 initialized ? ? ? ? ? ? ? ? initialized tgra_2 initialized ? ? ? ? ? ? ? ? initialized tgrb_2 initialized ? ? ? ? ? ? ? ? initialized tcr_0 initialized ? ? ? ? ? ? ? ? initialized tmr_0 tcr_1 initialized ? ? ? ? ? ? ? ? initialized tmr_1 tcsr_0 initialized ? ? ? ? ? ? ? ? initialized tmr_0 tcsr_1 initialized ? ? ? ? ? ? ? ? initialized tmr_1 tcora_0 initialized ? ? ? ? ? ? ? ? initialized tmr_0 tcora_1 initialized ? ? ? ? ? ? ? ? initialized tmr_1 tcorb_0 initialized ? ? ? ? ? ? ? ? initialized tmr_0 tcorb_1 initialized ? ? ? ? ? ? ? ? initialized tmr_1 tcnt_0 initialized ? ? ? ? ? ? ? ? initialized tmr_0 tcnt_1 initialized ? ? ? ? ? ? ? ? initialized tmr_1 tcsr_0 initialized ? ? ? ? ? ? ? ? initialized wdt_0 tcnt_0 initialized ? ? ? ? ? ? ? ? initialized rstcsr initialized ? ? ? ? ? ? ? ? initialized
section 24 list of registers rev. 5.00 sep. 01, 2009 page 595 of 656 rej09b0071-0500 register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module smr_0 initialized ? ? ? ? ? ? ? ? initialized sci_0 iccr_0 initialized ? ? ? ? ? ? ? ? initialized iic_0 brr_0 initialized ? ? ? ? ? ? ? ? initialized sci_0 icsr_0 initialized ? ? ? ? ? ? ? ? initialized iic_0 scr_0 initialized ? ? ? ? ? ? ? ? initialized sci_0 tdr_0 initialized ? ? ? initialized initialized initialized initialized initialized initialized ssr_0 initialized ? ? ? initialized initialized initialized initialized initialized initialized rdr_0 initialized ? ? ? initialized initialized initialized initialized initialized initialized scmr_0 initialized ? ? ? ? ? ? ? ? initialized icdr_0/ sarx_0 initialized ? ? ? ? ? ? ? ? initialized iic_0 icmr_0/ sar_0 initialized ? ? ? ? ? ? ? ? initialized smr_1 initialized ? ? ? ? ? ? ? ? initialized sci_1 iccr_1 * initialized ? ? ? ? ? ? ? ? initialized iic_1 brr_1 initialized ? ? ? ? ? ? ? ? initialized sci_1 icsr_1 * initialized ? ? ? ? ? ? ? ? initialized iic_1 scr_1 initialized ? ? ? ? ? ? ? ? initialized sci_1 tdr_1 initialized ? ? ? initialized initialized initialized initialized initialized initialized ssr_1 initialized ? ? ? initialized initialized in itialized initialized initialized initialized rdr_1 initialized ? ? ? initialized initialized initialized initialized initialized initialized scmr_1 initialized ? ? ? ? ? ? ? ? initialized icdr_1/ sarx_1 * initialized ? ? ? ? ? ? ? ? initialized iic_1 icmr_1/ sar_1 * initialized ? ? ? ? ? ? ? ? initialized addrah initialized ? ? ? initialized initialized in itialized initialized initialized initialized a/d addral initialized ? ? ? initialized initialized initialized initialized initialized initialized addrbh initialized ? ? ? initialized initialized initialized initialized initialized initialized addrbl initialized ? ? ? initialized initialized initialized initialized initialized initialized addrch initialized ? ? ? initialized initialized in itialized initialized initialized initialized addrcl initialized ? ? ? initialized initialized initialized initialized initialized initialized
section 24 list of registers rev. 5.00 sep. 01, 2009 page 596 of 656 rej09b0071-0500 register name reset high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby module addrdh initialized ? ? ? initialized initialized in itialized initialized initialized initialized a/d addrdl initialized ? ? ? initialized initialized initialized initialized initialized initialized adcsr initialized ? ? ? initialized initialized initialized initialized initialized initialized adcr initialized ? ? ? initialized initialized in itialized initialized initialized initialized tcsr_1 initialized ? ? ? ? ? ? ? ? initialized wdt_1 tcnt_1 initialized ? ? ? ? ? ? ? ? initialized flmcr1 * initialized ? ? ? ? ? ? ? initialized initialized flash flmcr2 * initialized ? ? ? ? ? ? ? initialized initialized ebr1 * initialized ? ? ? ? ? ? ? initialized initialized ebr2 * initialized ? ? ? ? ? ? ? initialized initialized flpwcr * initialized ? ? ? ? ? ? ? initialized initialized port1 initialized ? ? ? ? ? ? ? ? initialized port port3 initialized ? ? ? ? ? ? ? ? initialized port4 initialized ? ? ? ? ? ? ? ? initialized port7 initialized ? ? ? ? ? ? ? ? initialized port9 initialized ? ? ? ? ? ? ? ? initialized portf initialized ? ? ? ? ? ? ? ? initialized notes: ? is not initialized. * supported only by the h8s/2268 group.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 597 of 656 rej09b0071-0500 section 25 electrical characteristics 25.1 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 25.1. system clock (1) power supply voltage and range of oscillation frequency (condition a) condition a (f-ztat version): vcc = 3.0 to 5.5 v, avcc = 2.7 to 5.5 v, vref = 2.7 v to avcc, vss = avss = 0 v, = 32.768 khz, 2 to 13.5 mhz, ta = -20 to +75 (regular specification), ta = -40 to + 85 (wide range specification) condition b (masked rom version): vcc = 2.7 to 5.5 v, avcc = 2.7 to 5.5 v, vref = 2.7 v to avcc, vss = avss = 0 v, = 32.768 khz, 2 to 13.5 mhz, ta = -20 to +75 (regular specification), ta = -40 to + 85 (wide range specification) condition c (f-ztat version): vcc = 4.0 to 5.5 v, avcc = 4.0 to 5.5 v, vref = 4.0 v to avcc, vss = avss = 0 v, = 32.768 khz, 10 to 20.5 mhz, ta = -20 to +75 (regular specification), ta = -40 to + 85 (wide range specification) condition d (masked rom version): vcc = 4.0 to 5.5 v, avcc = 4.0 to 5.5 v, vref = 4.0 v to avcc, vss = avss = 0 v, = 32.768 khz, 10 to 20.5 mhz, ta = -20 to +75 (regular specification), ta = -40 to +85 (wide range specification) active (high-speed/medium-speed) mode sleep mode f (mhz) 20.5 13.5 2.0 0 2.7 3.0 4.0 5.5 vcc (v) sub clock sub clock aii operating modes system clock (2) power supply voltage and range of oscillation frequency (condition b) active (high-speed/medium-speed) mode sleep mode aii operating modes f (khz) 32.768 0 2.7 3.0 4.0 5.5 vcc (v) f (mhz) 20.5 13.5 2.0 0 2.7 3.0 4.0 5.5 vcc (v) f (khz) 32.768 0 2.7 3.0 4.0 5.5 vcc (v) figure 25.1 power supply voltage and operating ranges (1)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 598 of 656 rej09b0071-0500 48.8 74 500 0 2.7 3.0 4.0 5.5 30.5 0 2.7 3.0 4.0 5.5 48.8 74 500 0 2.7 3.0 4.0 5.5 30.5 0 2.7 3.0 4.0 5.5 48.8 74 100 500 0 2.7 3.0 4.0 5.5 30.5 0 2.7 3.0 4.0 5.5 20.5 13.5 10.0 2.0 0 2.7 3.0 4.0 5.5 32.768 0 2.7 3.0 4.0 5.5 system clock (3) power supply voltage and range of oscillation frequency (condition c and d) active (high-speed/medium-speed) mode sleep mode f (mhz) t (ns) vcc (v) sub clock aii operating modes f (khz) system clock (4) power supply voltage and range of instruction execution (condition a) active (high-speed/medium-speed) mode sub clock subactive mode t ( s) t (ns) system clock (5) power supply voltage and range of instruction execution (condition b) active (high-speed/medium-speed) mode sub clock subactive mode t ( s) vcc (v) vcc (v) vcc (v) vcc (v) vcc (v) t (ns) system clock (6) power supply voltage and range of instruction execution (condition c and d) active (high-speed/medium-speed) mode sub clock subactive mode t ( s) vcc (v) vcc (v) figure 25.1 power supply voltage and operating ranges (2)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 599 of 656 rej09b0071-0500 25.2 electrical characteristics of h8s/2268 group 25.2.1 absolute maximum ratings table 25.1 lists the absolute maximum ratings. table 25.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v cv cc ?0.3 to +4.3 v input voltage (except port 4, 9, ph7) v in ?0.3 to v cc + 0.3 v input voltage (port 4, 9, ph7) v in ?0.3 to av cc + 0.3 v reference voltage v ref ?0.3 to av cc + 0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?20 to +75 * c wide-range specifications: ?40 to +85 * c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded. note: * operating temperature range for flash memory programming/erasing is t a = ?20 to +75c.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 600 of 656 rej09b0071-0500 25.2.2 dc characteristics table 25.2 lists the dc characteristics. table 25.3 lists the permissible output currents. table 25.4 lists the bus drive characteristics. table 25.2 dc characteristics (1) condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.8 v vt + - vt ? v cc 0.05 ? ? v vcc = 4.0 to 5.5 v schmitt trigger input voltage irq0 , irq1 , irq3 to irq5 , wkp0 to wkp7 v cc 0.04 ? ? v vcc = 3.0 to 4.0 v input high voltage res , stby , nmi, fwe, md2, md1 v ih v cc 0.9 ? v cc + 0.3 v extal, ports 1, 3, 7, f, j to n, ph0 to ph3 v cc 0.8 ? v cc + 0.3 v ports 4 * 4 , 9, ph7 v cc 0.8 ? av cc + 0.3 * 4 v input low voltage res , stby , fwe, md2, md1 v il - 0.3 ? v cc 0.1 v nmi, extal, ports 1, 3, 4, 7, 9, f, h, j to n - 0.3 ? v cc 0.2 v v oh v cc - 0.5 ? ? v i oh = - 200 a all output pins except p34 and p35, ph0 to ph3, and ports j to n v cc - 1.0 ? ? v i oh = - 1 ma p34 and p35 * 2 v cc - 2.7 ? ? v i oh = - 100 a, v cc = 4.0 to 5.5 v v cc - 0.5 ? ? v i oh = - 200 a output high voltage ph0 to ph3, ports j to n v cc - 1.0 ? ? v i oh = - 1 ma, v cc = 4.0 to 5.5 v
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 601 of 656 rej09b0071-0500 item symbol min. typ. m ax. unit test conditions all output pins * 3 v ol ? ? 0.4 v i ol = - 0.8 ma i ol = 5 ma output low voltage port 7 ? ? 1.0 v i ol = 10 ma, v cc = 4.0 to 5.5 v res ? ? 1.0 a stby , nmi, fwe, md2, md1 ? ? 1.0 a v in = 0.5 to v cc - 0.5 v ports 4, 9 ? ? 1.0 a v in = 0.5 to av cc - 0.5 v input leakage current ph7 | l in | ? ? 1.0 a v in = 0.5 to av cc - 0.5 v three-state leakage current (off state) ports 1, 3, 7, f, j to n, ph0 to ph3 | l tsi | ? ? 1.0 a v in = 0.5 to av cc - 0.5 v input pull-up mos current port j ?l p 10 ? 300 a v in = 0 v notes: 1. if the a/d and d/a converters and dtmf generation circuit are not used, do not leave the avcc, vref, and avss pins open. apply a voltage 2.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. p35/sck1/scl0 and p34/sda0 are nmos push-pull outputs. to output high level signal from scl0 and sda0 (ice = 1), pull-up resistance must be connected externally. p35/sck1 and p34 (ice = 0) are driven high by nmos. to output high, pull-up resistance should be connected externally. 3. when ice = 0. to output low when bus drive function is selected is determined in table 25.4, bus drive characteristics. 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 602 of 656 rej09b0071-0500 table 25.2 dc characteristics (2) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.8 v schmitt trigger input voltage irq0 , irq1 , irq3 to irq5 , wkp0 to wkp7 vt + - vt ? v cc 0.05 ? ? v input high voltage res , stby ,nmi, fwe, md2, md1 v ih v cc 0.9 ? v cc + 0.3 v extal, ports 1, 3, 7, f, j to n, ph0 to ph3 v cc 0.8 ? v cc + 0.3 v ports 4 * 4 , 9, ph7 v cc 0.8 ? v cc + 0.3 * 4 v input low voltage res , stby ,fwe, md2, md1 v il - 0.3 ? v cc 0.1 v nmi, extal, ports 1, 3, 4, 7, 9, f, h, j to n - 0.3 ? v cc 0.2 v output high voltage v oh v cc - 0.5 ? ? v i oh = - 200 a all output pins except p34 and p35, ph0 to ph3, and ports j to n v cc - 1.0 ? ? v i oh = - 1 ma p34 and p35 * 2 v cc - 2.7 ? ? v i oh = - 100 a v cc - 0.5 ? ? v i oh = - 200 a ph0 to ph3, ports j to n v cc - 1.0 ? ? v i oh = - 1 ma all output pins * 3 v ol ? ? 0.4 v i ol = 0.8 ma output low voltage port 7 ? ? 1.0 v i ol = 10 ma res ? ? 1.0 a stby , nmi, fwe, md2, md1 ? ? 1.0 a v in = 0.5 to v cc - 0.5 v input leakage current ports 4, 9 | l in | ? ? 1.0 a v in = 0.5 to av cc - 0.5 v ph7 ? ? 1.0 a v in = 0.5 to av cc - 0.5 v
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 603 of 656 rej09b0071-0500 item symbol min. typ. m ax. unit test conditions three-state leakage current (off state) ports 1, 3, 7, ports f, j to n, ph0 to ph3 | l tsi | ? ? 1.0 a v in = 0.5 to av cc - 0.5 v input pull-up mos current port j ?l p 50 ? 300 a v in = 0 v notes: 1. if the a/d and d/a converters and dtmf generation circuit are not used, do not leave the avcc, vref, and avss pins open. apply a voltage 4.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. p35/sck1/scl0 and p34/sda0 are nmos push-pull outputs. to output high level signal from scl0 and sda0 (ice = 1), pull-up resistors must be connected externally. p35/sck1 and p34 (ice = 0) are driven high by nmos. to output high, pull-up resistors should be connected externally. 3. when ice = 0. to output low when bus drive function is selected is determined in table 25.4, bus drive characteristics. 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 604 of 656 rej09b0071-0500 table 25.2 dc characteristics (3) condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. max. unit test conditions res c in ? ? 30 pf nmi ? ? 30 pf p32 to p35 ? ? 20 pf input capacitance all input pins except res , nmi, p32 to p35 ? ? 15 pf v in = 0 v, f = 1 mhz, ta = 25c current consumption * 2 normal operation i cc * 4 ? 18 v cc = 3.0 v 30 v cc = 5.5 v ma f = 13.5 mhz sleep mode ? 13 v cc = 3.0 v 22 v cc = 5.5 v ma f = 13.5 mhz all modules stopped ? 10 ? ma f = 13.5 mhz, v cc = 3.0 v (reference values) medium-speed mode ( /32) ? 12 ? ma f = 13.5 mhz, v cc = 3.0 v (reference values) subactive mode ? 60 110 a using 32.768 khz crystal resonator, vcc = 3.0 v (lcd lighting) subsleep mode ? 50 90 a using 32.768 khz crystal resonator, vcc = 3.0 v (lcd lighting) watch mode ? 4 25 a using 32.768 khz crystal resonator, vcc = 3.0 v (lcd and tmr4 not used, wdt_1 operates)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 605 of 656 rej09b0071-0500 item symbol min. typ. max. unit test conditions ? 0.5 vcc = 3.0 v 10 vcc = 5.5 v a t a 50c, 32.768 khz not used current consumption * 2 standby mode * 3 i cc * 4 ? ? 50 vcc = 5.5 v 50c < t a , 32.768 khz not used analog power supply current during a/d conversion, d/a conversion, dtmf output al cc ? 1.0 2.4 ma waiting for a/d conversion, d/a conversion, dtmf stopped ? 0.01 5.0 a reference current during a/d conversion, d/a conversion al cc ? 1.0 2.2 ma waiting for a/d conversion, d/a conversion ? 0.01 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters and dtmf generation circuit are not used, do not leave the avcc, vref, and avss pins open. apply a voltage 2.0 to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. current consumption values are for v ih min. = v cc ? 0.2 v, v il max. = 0.2 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih min. = v cc ? 0.2, and v il max. = 0.2 v. 4. i cc depends on v cc and f as follows (reference): i cc max. = 4.0 (ma) + 0.64 (ma/v) vcc + 0.75 (ma/mhz) f + 0.15 (ma/(mhz v)) v cc f (normal operation) i cc max. = 3.0 (ma) + 0.60 (ma/v) vcc + 0.60 (ma/mhz) f + 0.10 (ma/(mhz v)) v cc f (sleep mode)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 606 of 656 rej09b0071-0500 table 25.2 dc characteristics (4) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions res c in ? ? 30 pf nmi ? ? 30 pf p32 to p35 ? ? 20 pf input capacitance all input pins except res , nmi, p32 to p35 ? ? 15 pf v in = 0 v, f = 1 mhz, ta = 25c current consumption * 2 normal operation i cc * 4 ? 30 v cc = 5.0 v 40 v cc = 5.5 v ma f = 20.5 mhz sleep mode ? 22 v cc = 5.0 v 30 v cc = 5.5 v ma f = 20.5 mhz all modules stopped ? 15 ? ma f = 20.5 mhz, v cc = 5.0 v (reference values) medium-speed mode ( /32) ? 19 ? ma f = 20.5 mhz, v cc = 5.0 v (reference values) subactive mode ? 70 120 a using 32.768 khz crystal resonator, vcc = 5.0 v (lcd lighting) subsleep mode ? 60 100 a using 32.768 khz crystal resonator, vcc = 5.0 v (lcd lighting) watch mode ? 5 30 a using 32.768 khz crystal resonator, vcc = 5.0 v (lcd and tmr4 not used, wdt_1 operates) standby mode * 3 ? 1.0 vcc = 5.0 v 10 vcc = 5.5 v a t a 50c, 32.768 khz not used ? ? 50 vcc = 5.5 v 50c < t a , 32.768 khz not used
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 607 of 656 rej09b0071-0500 item symbol min. typ. m ax. unit test conditions analog power supply current during a/d conversion, d/a conversion, dtmf output al cc ? 1.5 2.5 ma waiting for a/d conversion, d/a conversion, dtmf stopped ? 0.01 5.0 a reference current during a/d conversion, d/a conversion al cc ? 1.5 2.2 ma waiting for a/d conversion, d/a conversion ? 0.01 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters and dtmf generation circuit are not used, do not leave the avcc, vref, and avss pins open. apply a voltage 4.0 to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. current consumption values are for v ih min. = v cc ? 0.2 v, v il max. = 0.2 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 4.0 v, v ih min. = v cc ? 0.2, and v il max. = 0.2 v. 4. i cc depends on v cc and f as follows (reference): i cc max. = 4.0 (ma) + 0.64 (ma/v) vcc + 0.75 (ma/mhz) f + 0.15 (ma/(mhz v)) v cc f (normal operation) i cc max. = 3.0 (ma) + 0.60 (ma/v) vcc + 0.60 (ma/mhz) f + 0.10 (ma/(mhz v)) v cc f (sleep mode)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 608 of 656 rej09b0071-0500 table 25.3 permissible output currents condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit port 7 i ol ? ? 10 ma permissible output low current (per pin) scl1, scl0, sda1, sda0 ? ? 10 ma output pins except port 7, scl1, scl0, sda1, sda0 ? ? 1.0 ma total of port 7 i ol ? ? 30 ma permissible output low current (total) total of all output pins including port 7 ? ? 60 ma permissible output high current (per pin) all output pins ?i oh ? ? 1.0 ma permissible output high current (total) total of all output pins ?i oh ? ? 30 ma note: to protect chip reliability, do not exceed the output current values in table 25.3.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 609 of 656 rej09b0071-0500 table 25.4 bus drive characteristics (1) condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 , target pins: scl1, scl 0 , sda1, sda 0 item symbol min. typ. max. unit test conditions vt ? v cc 0.3 ? ? v schmitt trigger input voltage vt + ? ? v cc 0.7 0.4 ? ? v cc = 4.0 to 5.5 v vt + - vt ? v cc 0.05 ? ? v cc = 3.0 to 4.0 v input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il -0.5 ? v cc 0.3 v ? ? 0.5 v i ol = 8 ma, v cc = 4.0 to 5.5 v output low voltage v ol ? ? 0.4 i ol = 3 ma input capacitance c in ? ? 20 pf vin = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | l sti | ? ? 1.0 a v in = 0.5 to v cc -0.5 sdl, sda output fall time t of 20 + 0.1 cb ? 250 ns note: if the a/d and d/a converters and dtmf generation circuit are not used, do not leave the avcc, vref, and avss pins open. apply a voltage 2.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 610 of 656 rej09b0071-0500 table 25.4 bus drive characteristics (2) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 , target pins: scl1, scl 0 , sda1, sda 0 item symbol min. typ. max. unit test conditions vt ? v cc 0.3 ? ? v schmitt trigger input voltage vt + ? ? v cc 0.7 vt + - vt ? 0.4 ? ? input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il -0.5 ? v cc 0.3 v ? ? 0.5 v i ol = 8 ma output low voltage v ol ? ? 0.4 i ol = 3 ma input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | l sti | ? ? 1.0 a v in = 0.5 to v cc - 0.5 sdl, sda output fall time t of 20 + 0.1cb ? 250 ns note: if the a/d and d/a converters and dtmf generation circuit are not used, do not leave the avcc, vref, and avss pins open. apply a voltage 4.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc 25.2.3 ac characteristics figure 25.2 show, the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 30 pf: r l = 2.4 k r h = 12 input/output timing measurement levels ? low level : 0.8 v ? high level : 2.0 v figure 25.2 output load circuit
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 611 of 656 rej09b0071-0500 clock timing: table 25.5 lists the clock timing. table 25.5 clock timing condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition c 13.5 mhz 20.5 mhz item symbol min. typ. max. min. typ. max. unit test conditions clock cycle time t cyc 74 ? 500 48.8 ? 100 ns clock oscillator settling time at reset (crystal) t osc1 20 ? ? 10 ? ? ms figure 25.4 clock oscillator settling time in software standby (crystal) t osc2 8 ? ? 8 ? ? ms figure 22.3 external clock settling delay time t dext 500 ? ? 500 ? ? s figure 25.4 sub clock oscillator settling time t osc3 ? ? 2 ? ? 2 s sub clock oscillator frequency f sub ? 32.768 ? ? 32.768 ? khz sub clock ( sub ) cycle time t sub ? 30.5 ? ? 30.5 ? s
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 612 of 656 rej09b0071-0500 control signal timing: table 25.6 lists the control signal timing. table 25.6 control signal timing condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. max. unit test conditions res pulse width t resw 20 ? t cyc figure 25.5 nmi pulse width (exiting software standby mode) t nmiw 200 ? ns figure 25.6 irq pulse width (exiting software standby mode) t irqw 200 ? ns
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 613 of 656 rej09b0071-0500 timing of on-chip peripheral modules: table 25.7 lists the timing of on-chip peripheral modules. table 25.8 lists the i 2 c bus timing. table 25.7 timing of on-chip peripheral modules condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition c item symbol min. max. min. max. unit test conditions tpu single edge t tckwh 1.5 ? 1.5 ? t cyc figure 25.7 timer clock pulse width both edges t tckwl 2.5 ? 2.5 ? single edge t tmcwh 1.5 ? 1.5 ? tmr_0 to tmr_3 timer clock pulse width both edges t tmcwl 2.5 ? 2.5 ? t cyc figure 25.8 tmr_4 timer clock pulse width t tmcwh t tmcwl 1.5 ? 1.5 ? t cyc sci asynchronous t scyc ? 4 ? t cyc figure 25.9 input clock cycle synchronous ? 6 ? input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckf ? 1.5 ? 1.5 t cyc input clock fall time t sckf ? 1.5 ? 1.5 transmit data delay time t txd ? 75 ? 50 ns figure 25.10 receive data setup time (synchronous) t rxs 75 ? 50 ? ns receive data hold time (synchronous) t rxh 75 ? 50 ? ns
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 614 of 656 rej09b0071-0500 table 25.8 i 2 c bus timing condition: v cc = 3.0 v to 5.5 v, v ss = 0 v, = 5 mhz to maximum operating frequency t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit test conditions remarks scl input cycle time t scl 12 t cyc ? ? ns scl input high pulse width t sclh 3 t cyc ? ? ns scl input low pulse width t scll 5 t cyc ? ? ns scl, sda input rise time t sr ? ? 7.5 t cyc * ns scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse elimination time t sp ? ? 1 t cyc ns sda input bus free time t buf 5 t cyc ? ? ns start condition input hold time t stah 3 t cyc ? ? ns retransmission start condition input setup time t stas 3 t cyc ? ? ns stop condition input setup time t stos 3 t cyc ? ? ns data input setup time t sdas 0.5 t cyc ? ? ns data input hold time t sdah 0 ? ? ns figure 25.11 scl, sda load capacitance c b ? ? 400 pf note: * t sr can be set to 7.5 t cyc or 17.5 t cyc according to the clock used for the i 2 c module. for details, see section 14.6 usage notes.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 615 of 656 rej09b0071-0500 25.2.4 a/d conversion characteristics table 25.9 lists the a/d conversion characteristics. table 25.9 a/d conversion characteristics condition a (f-ztat version): v cc = 3.0 v to 5.5 v * , av cc = 2.7 v to 5.5 v * , v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v * , av cc = 4.0 v to 5.5 v * , v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition c 13.5 mhz 20.5 mhz item min. typ. max. min. typ. max. unit resolution 10 10 10 10 10 10 bits conversion time 9.6 ? ? 6.3 ? ? s analog input capacitance ? ? 20 ? ? 20 pf permissible signal-source impedance ? ? 5 ? ? 5 k nonlinearity error ? ? 6.0 ? ? 3.0 lsb offset error ? ? 4.0 ? ? 2.0 lsb full-scale error ? ? 4.0 ? ? 2.0 lsb quantization error ? ? 0.5 ? ? 0.5 lsb absolute accuracy ? ? 8.0 ? ? 4.0 lsb note: * an0 and an1 can be used only when vcc = avcc.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 616 of 656 rej09b0071-0500 25.2.5 d/a conversion characteristics table 25.10 lists the d/a conversion characteristics. table 25.10 d/a conversion characteristics condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a and c item min. typ. max. unit test conditions resolution 8 8 8 bits conversion time ? ? 10 s load capacitance: 20 pf absolute accuracy * ? 2.0 3.0 lsb load resistance: 2 m ? ? 2.0 lsb load resistance: 4 m note: * does not apply to module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 617 of 656 rej09b0071-0500 25.2.6 lcd characteristics table 25.11 lists the lcd characteristics. table 25.11 lcd characteristics condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition c standard value standard value item symbol applicable pins test conditions min. typ. max. min. typ. max. unit notes segment driver step-down voltage v ds seg1 to seg40 id = 2 a ? ? 0.6 ? ? 0.6 v * 1 common driver step-down voltage v dc com1 to com4 id = 2 a ? ? 0.3 ? ? 0.3 v * 1 lcd power supply division resistor r lcd between v1 and v ss 40 360 1000 40 360 1000 k lcd voltage (step- up voltage circuit not used) v lcd v1 3.0 * 4 ? v cc 4.0 ? v cc v * 2 lcd input reference voltage (using step-up voltage circuit) * 3 v lcd3 v3 1.0 1.67 1.83 ? ? ? v v lcd2 v2 ? 2 v lcd3 ? ? ? ? lcd voltage (using step-up voltage circuit) * 3 v lcd1 v1 no load ? 3 v lcd3 ? ? ? ? v reference value lcd input reference power supply current (using step-up voltage circuit) * 3 i lcd3 v3 no load, frame frequency: 64 hz, v lcd3 = 1.67 v ? 2.0 ? ? ? ? a reference value notes: 1. voltage step-down between power supply pins v1, v2, v3, and vss and segment pins. 2. if the lcd voltage is provided by an external power supply, the following relationship must be maintained: v cc v1 v2 v3 v ss . 3. the step-up voltage circuit should be used with 1/3 duty or 1/4 duty. 4. when the step-up voltage circuit is not used, the lowest value is v1 = 3.0 v. use the step-up voltage circuit when v1 < 3.0 v.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 618 of 656 rej09b0071-0500 25.2.7 dtmf characteristics table 25.12 lists the dtmf characteristics. table 25.12 dtmf characteristics condition a (f-ztat version): v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 to 13.2 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition c (f-ztat version): v cc = 4.0 v to 5.5 v, av cc = 2.7 v * 1 to 5.5 v, v ref = 2.7 v * 1 to av cc , v ss = av ss = 0 v, = 10 to 20.4 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) standard value item symbol applicable pins test conditions min. typ. max. unit notes dtmf output voltage (row side) v or toned av cc -gnd = 2.7 v r l = 100 k 750 924 ? mvrms figure 25.12 * 2 dtmf output voltage (column side) v oc toned av cc - gnd = 2.7 v r l = 100 k 770 945 ? mvrms figure 25.12 * 2 dtmf output distortion % disdt toned av cc ? gnd = 2.7 v r l = 100 k ? 3 7 % figure 25.12 dtmf output ratio db cr toned av cc ? gnd = 2.7 v r l = 100 k ? 2.5 ? db figure 25.12 notes: 1. when av cc = 2.7 to 4.0 v, and v ref = 2.7 to 4.0 v, dtmf is only available. 2. v or and v cc are output voltages when a single waveform is output.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 619 of 656 rej09b0071-0500 25.2.8 flash memory characteristics table 25.13 shows the flash memory characteristics. table 25.13 flash memory characteristics condition: v cc = 3.0 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?25c to +75c (programming/erasing operating temperature range: regular specification) item symbol min. typ. max. unit test condition programming time * 1 * 2 * 4 t p ? 30 200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block count of rewriting n wec 100 * 6 10000 * 7 ? times data retention time t drp * 8 10 ? ? year programming wait time after swe1 bit setting * 1 t sswe 1 1 ? s wait time after psu1 bit setting * 1 t spsu 50 50 ? s wait time after p1 bit setting * 1 * 4 t sp10 8 10 12 s t sp30 28 30 32 s 6 n 1 t sp200 198 200 202 s 1000 n 7 wait time after p1 bit clear * 1 t cp 5 5 ? s wait time after psu1 bit clear * 1 t cpsu 4 4 ? s wait time after pv1 bit setting * 1 t spv 2 2 ? s wait time after h'ff dummy write * 1 t spvr 2 2 ? s wait time after pv1 bit clear * 1 t cpv 100 100 ? s wait time after swe1 bit clear t cswe ? ? ? s n1 ? ? 6 * 4 times maximum programming count * 1 * 4 n2 ? ? 994 * 4 times erase wait time after swe1 bit setting * 1 t sswe 1 1 ? s wait time after esu1 bit setting * 1 t sesu 100 100 ? s wait time after e1 bit setting * 1 * 5 t se 10 10 100 ms wait time after e1 bit clear * 1 t ce 10 10 ? s wait time after esu1 bit clear * 1 t cesu 10 10 ? s wait time after ev1 bit setting * 1 t sev 20 20 ? s wait time after h'ff dummy write * 1 t sevr 2 2 ? s wait time after ev1 bit clear * 1 t cev 4 4 ? s wait time after swe1 bit clear t cswe 100 100 ? s maximum erase count * 1 * 5 n ? ? 100 times
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 620 of 656 rej09b0071-0500 notes: 1. make each time setting in accordance with the program or erase algorithm. 2. programming time per 128 bytes (shows the total period for which the p1 bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e1 bit in flmcr1 is set. it does not include the erase verification time.) 4. the maximum programming time value (t p (max.)): t p (max.) = wait time after p1 bit setting (t sp ) maximum programming count (n) (t sp30 + t sp10 ) 6 + (t sp200 ) 994 5. for the maximum erase time (t e (max.)), the following relationship applies between the wait time after e1 bit setting (t se ) and the maximum erase count (n): t e (max.) = wait time after e1 bit setting (t se ) maximum erase count (n) 6. the minimum times that all characteristics after rewriting are guaranteed. (a range between 1 and minimum value is guaranteed.) 7. the reference value at 25 c. (normally, it is a reference that rewriting is enabled up to this value.) 8. data hold characteristics when rewriting is performed within the range of specifications including minimum value.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 621 of 656 rej09b0071-0500 25.3 electrical characteristics of h8s/2264 group 25.3.1 absolute maximum ratings table 25.14 lists the absolute maximum ratings. table 25.14 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v cv cc ?0.3 to +4.3 v input voltage (except ports 4 and 9) v in ?0.3 to v cc + 0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc + 0.3 v reference voltage v ref ?0.3 to av cc + 0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 622 of 656 rej09b0071-0500 25.3.2 dc characteristics table 25.15 lists the dc characteristics. table 25.16 lists the permissible output currents. table 25.17 lists the bus drive characteristics. table 25.15 dc characteristics (1) condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.8 v vt + - vt ? v cc 0.05 ? ? v vcc = 4.0 to 5.5 v schmitt trigger input voltage irq0 , irq1 , irq3 , irq4 , wkp0 to wkp7 v cc 0.04 ? ? v vcc = 2.7 to 4.0 v input high voltage res , stby , nmi, fwe, md2, md1 v ih v cc 0.9 ? v cc + 0.3 v extal, ports 1, 3, 7, f, h, j to l v cc 0.8 ? v cc + 0.3 v ports 4 * 4 , 9 v cc 0.8 ? av cc + 0.3 * 4 v input low voltage res , stby , fwe, md2, md1 v il - 0.3 ? v cc 0.1 v nmi, extal, ports 1, 3, 4, 7, 9, f, h, j to l - 0.3 ? v cc 0.2 v output high voltage v oh v cc ? 0.5 ? ? v i oh = - 200 a all output pins except p34 and p35 v cc ? 1.0 ? ? v i oh = - 1 ma p34 and p35 * 2 v cc ? 2.7 ? ? v i oh = - 100 a, v cc = 4.0 to 5.5 v all output pins * 3 v ol ? ? 0.4 v i ol = 0.8 ma output low voltage port 7 ? ? 1.0 v i ol = 5 ma i ol = 10 ma, v cc = 4.0 to 5.5 v
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 623 of 656 rej09b0071-0500 item symbol min. typ. m ax. unit test conditions res ? ? 1.0 a stby , nmi, fwe, md2, md1 ? ? 1.0 a v in = 0.5 to v cc - 0.5 v ports 4, 9 ? ? 1.0 a v in = 0.5 to av cc - 0.5 v input leakage current ph7 | l in | ? ? 1.0 a v in = 0.5 to v cc - 0.5 v three-state leakage current (off state) ports 1, 3, 7, f, j to l, ph0 to ph3 | l tsi | ? ? 1.0 a v in = 0.5 to v cc - 0.5 v input pull-up mos current port j ?l p 10 ? 300 a v in = 0 v notes: 1. if the a/d converter is not used, do not leave the avcc, vref, and avss pins open. apply a voltage 2.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. p35/sck1/scl0 and p34/sda0 are nmos push-pull outputs. to output high level signal from scl0 and sda0 (ice = 1), pull-up resistors must be connected externally. p35/sck1 and p34 (ice = 0) are driven high by nmos. to output high pull-up resistors should be connected externally. 3. when ice = 0. the output low level when bus drive function is selected is indicated in table 25.17, bus drive characteristics. 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 624 of 656 rej09b0071-0500 table 25.15 dc characteristics (2) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions vt - v cc 0.2 ? ? v vt + ? ? v cc 0.8 v schmitt trigger input voltage irq0 , irq1 , irq3 , irq4 , wkp0 to wkp7 vt + - vt - v cc 0.05 ? ? v input high voltage res , stby ,nmi, fwe, md2, md1 v ih v cc 0.9 ? v cc + 0.3 v extal, ports 1, 3, 7, f, h, j to l v cc 0.8 ? v cc + 0.3 v ports 4 * 4 , 9 v cc 0.8 ? av cc + 0.3 * 4 v input low voltage res , stby ,fwe, md2, md1 v il - 0.3 ? v cc 0.1 v nmi, extal, ports 1, 3, 4, 7, 9, f, h, j to l - 0.3 ? v cc 0.2 v v oh v cc - 0.5 ? ? v i oh = - 200 a output high voltage all output pins except p34 and p35 v cc - 1.0 ? ? v i oh = - 1 ma p34 and p35 * 2 v cc - 2.7 ? ? v i oh = - 100 a all output pins * 3 v ol ? ? 0.4 v i ol = 0.8 ma output low voltage port 7 ? ? 1.0 v i ol = 10 ma res ? ? 1.0 a stby , nmi, fwe, md2, md1 ? ? 1.0 a v in = 0.5 to v cc - 0.5 v ports 4, 9 ? ? 1.0 a v in = 0.5 to av cc - 0.5 v input leakage current ph7 | l in | ? ? 1.0 a v in = 0.5 to v cc - 0.5 v three-state leakage current (off state) ports 1, 3, 7, f, j to l, ph0 to ph3 | l tsi | ? ? 1.0 a v in = 0.5 to v cc - 0.5 v input pull-up mos current port j ?l p 50 ? 300 a v in = 0 v
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 625 of 656 rej09b0071-0500 notes: 1. if the a/d converter is not used, do not leave the avcc, vref, and avss pins open. apply a voltage 4.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. p35/sck1/scl0 and p34/sda0 are nmos push-pull outputs. to output high level signal from scl0 and sda0 (ice = 1), pull-up resistors must be connected externally. p35/sck1 and p34 (ice = 0) are driven high by nmos. to output high pill-up resistors should be connected externally. 3. when ice = 0. the output low level when bus drive function is selected is indicated in table 25.17, bus drive characteristics. 4. when vcc < avcc, the maximum value for p40 and p41 is vcc + 0.3 v. table 25.15 dc characteristics (3) condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions res c in ? ? 30 pf nmi ? ? 30 pf p34 and p35 ? ? 20 pf input capacitance all input pins except res , nmi, p34, and p35 ? ? 15 pf v in = 0 v, f = 1 mhz, ta = 25c current consumption * 2 normal operation i cc * 4 ? 11 v cc = 3.0 v 18 v cc = 5.5 v ma f = 13.5 mhz sleep mode ? 7 v cc = 3.0 v 12.5 v cc = 5.5 v ma f = 13.5 mhz all modules stopped ? 7 ? ma f = 13.5 mhz, v cc = 3.0 v (reference values) medium- speed mode ( /32) ? 6 ? ma f = 13.5 mhz, v cc = 3.0 v (reference values) subactive mode ? 20 40 a using 32.768 khz crystal resonator, vcc = 3.0 v (lcd lighting) subsleep mode ? 8 25 a using 32.768 khz crystal resonator, vcc = 3.0 v (lcd lighting)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 626 of 656 rej09b0071-0500 item symbol min. typ. m ax. unit test conditions current consumption * 2 watch mode i cc * 4 ? 2.5 8 a t a 50c, using 32.768 khz crystal resonator, vcc = 3.0 v (lcd not used, wdt_1 operates) ? ? 10 50c < ta, using 32.768 khz crystal resonator, vcc = 3.0 v (lcd not used, wdt_1 operates) ? 0.5 vcc = 3.0 v 5 vcc = 5.5 v a t a 50c, 32.768 khz not used standby mode * 3 ? ? 20 vcc = 5.5 v 50c < t a , 32.768 khz not used during a/d conversion al cc ? 0.3 1.5 ma analog power supply current waiting for a/d conversion ? 0.01 5.0 a reference current during a/d conversion al cc ? 0.4 1.0 ma waiting for a/d conversion ? 0.01 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d converter is not used, do not leave the avcc, vref, and avss pins open. apply a voltage 2.0 to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. current consumption values are for v ih min. = v cc ? 0.2 v, v il max. = 0.2 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min. = v cc ? 0.2, and v il max. = 0.2 v. 4. i cc depends on v cc and f as follows (reference): i cc max. = 3.0 (ma) + 1.24 (ma/v) (vcc ? 2.7 (v)) + 1.00 (ma/mhz) (f ? 2.0 (mhz)) (normal operation) i cc max. = 2.0 (ma) + 1.12 (ma/v) (vcc ? 2.7 (v)) + 0.64 (ma/mhz) (f ? 2.0 (mhz)) (sleep mode)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 627 of 656 rej09b0071-0500 table 25.15 dc characteristics (4) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. m ax. unit test conditions res c in ? ? 30 pf nmi ? ? 30 pf p34 and p35 ? ? 20 pf input capacitance all input pins except res , nmi, p34, and p35 ? ? 15 pf v in = 0 v, f = 1 mhz, ta = 25c current consumption * 2 normal operation i cc * 4 ? 18 v cc = 5.0 v 25 v cc = 5.5 v ma f = 20.5 mhz sleep mode ? 12 v cc = 5.0 v 17 v cc = 5.5 v ma f = 20.5 mhz all modules stopped ? 11 ? ma f = 20.5 mhz, v cc = 5.0 v (reference values) medium- speed mode ( /32) ? 10 ? ma f = 20.5 mhz, v cc = 5.0 v (reference values) subactive mode ? 20 40 a using 32.768 khz crystal resonator, vcc = 5.0 v (lcd lighting) subsleep mode ? 8 25 a using 32.768 khz crystal resonator, vcc = 5.0 v (lcd lighting) watch mode ? 3 10 a t a 50c, using 32.768 khz crystal resonator, vcc = 5.0 v (lcd not used, wdt_1 operates)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 628 of 656 rej09b0071-0500 item symbol min. typ. m ax. unit test conditions current consumption * 2 watch mode i cc * 4 ? ? 12 a 50c < ta, using 32.768 khz crystal resonator, vcc = 5.0 v (lcd not used, wdt_1 operates) ? 0.5 vcc = 5.0 v 5 vcc = 5.5 v a t a 50c, 32.768 khz not used standby mode * 3 ? ? 20 vcc = 5.5 v 50c < t a , 32.768 khz not used during a/d conversion al cc ? 0.8 1.6 ma analog power supply current waiting for a/d conversion ? 0.01 5.0 a reference current during a/d conversion al cc ? 0.6 1.0 ma waiting for a/d conversion ? 0.01 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d converter is not used, do not leave the avcc, vref, and avss pins open. apply a voltage 4.0 to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 2. current consumption values are for v ih min. = vcc ? 0.2 v, v il max. = 0.2 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 4.0 v, v ih min. = v cc ? 0.2, and v il max. = 0.2 v. 4. i cc depends on v cc and f as follows (reference): i cc max. = 3.0 (ma) + 1.24 (ma/v) (vcc ? 2.7 (v)) + 1.00 (ma/mhz) (f ? 2.0 (mhz)) (normal operation) i cc max. = 2.0 (ma) + 1.12 (ma/v) (vcc ? 2.7 (v)) + 0.64 (ma/mhz) (f ? 2.0 (mhz)) (sleep mode)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 629 of 656 rej09b0071-0500 table 25.16 permissible output currents condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit port 7 i ol ? ? 10 ma permissible output low current (per pin) scl0, sda0 ? ? 10 ma output pins except port 7, scl0, sda0 ? ? 1.0 ma total of port 7 i ol ? ? 30 ma permissible output low current (total) total of all output pins including port 7 ? ? 60 ma permissible output high current (per pin) all output pins ?i oh ? ? 1.0 ma permissible output high current (total) total of all output pins ?i oh ? ? 30 ma note: to protect chip reliability, do not exceed the output current values in table 25.16.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 630 of 656 rej09b0071-0500 table 25.17 bus drive characteristics (1) condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * , target pins: scl 0 , sda 0 item symbol min. typ. max. unit test conditions schmitt trigger input voltage vt - v cc 0.3 ? ? v vt + ? ? v cc 0.7 0.4 ? ? v cc = 4.5 to 5.5 v vt + - vt - v cc 0.05 ? ? v cc = 2.7 to 4.5 v input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il -0.5 ? v cc 0.3 v ? ? 0.5 v i ol = 8 ma, v cc = 4.5 to 5.5 v output low voltage v ol ? ? 0.4 i ol = 3 ma input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | l tsi | ? ? 1.0 a v in = 0.5 to v cc -0.5 sdl, sda output fall time t of 20 + 0.1 cb ? 250 ns note: * if the a/d converter is not used, do not leave the avcc, vref, and avss pins open. apply a voltage 2.7 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc .
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 631 of 656 rej09b0071-0500 table 25.17 bus drive characteristics (2) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * , target pins: scl 0 , sda 0 item symbol min. typ. max. unit test conditions vt ? v cc 0.3 ? ? v schmitt trigger input voltage vt + ? ? v cc 0.7 vt + - vt ? 0.4 ? ? v cc = 4.5 to 5.5 v v cc 0.05 ? ? v cc = 4.0 to 4.5 v input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il -0.5 ? v cc 0.3 v ? ? 0.5 v i ol = 8ma output low voltage v ol ? ? 0.4 i ol = 3ma input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | l tsi | ? ? 1.0 a v in = 0.5 to v cc -0.5 sdl, sda output fall time t of 20 + 0.1cb ? 250 ns note: * if the a/d converter is not used, do not leave the avcc, vref, and avss pins open. apply a voltage 4.0 v to 5.5 v to the avcc and vref pins by connecting them to v cc , for instance. set v ref av cc . 25.3.3 ac characteristics figure 25.3 shows the test conditi ons for the ac characteristics. 5 v r l r h c lsi output pin c = 30 pf r l = 2.4 k r h = 12 input/output timing measurement levels ? low level : 0.8 v ? high level : 2.0 v figure 25.3 output load circuit
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 632 of 656 rej09b0071-0500 clock timing: table 25.18 lists the clock timing. table 25.18 clock timing condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) condition b condition d 13.5 mhz 20.5 mhz item symbol min. typ. max. min. typ. max. unit test conditions clock cycle time t cyc 74 ? 500 48.8 ? 100 ns clock oscillator settling time at reset (crystal) t osc1 20 ? ? 10 ? ? ms figure 25.4 clock oscillator settling time in software standby (crystal) t osc2 8 ? ? 8 ? ? ms figure 22.3 external clock settling time t dext 500 ? ? 500 ? ? s figure 25.4 sub clock oscillator settling time t osc3 ? ? 2 ? ? 2 s sub clock oscillator frequency f sub ? 32.768 ? ? 32.768 ? khz sub clock ( sub ) cycle time t sub ? 30.5 ? ? 30.5 ? s
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 633 of 656 rej09b0071-0500 control signal timing: table 25.19 lists the control signal timing. table 25.19 control signal timing condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) item symbol min. max. unit test conditions res pulse width t resw 20 ? t cyc figure 25.5 nmi pulse width (exiting software standby mode) t nmiw 200 ? ns figure 25.6 irq pulse width (exiting software standby mode) t irqw 200 ? ns
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 634 of 656 rej09b0071-0500 timing of on-chip peripheral modules: table 25.20 lists the timing of on-chip peripheral modules. table 25.21 lists the i 2 c bus timing. table 25.20 timing of on-chip peripheral modules condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) condition b condition d item symbol min. max. min. max. unit test conditions tpu single edge t tckwh 1.5 ? 1.5 ? t cyc figure 25.7 timer clock pulse width both edges t tckwl 2.5 ? 2.5 ? single edge t tmcwh 1.5 ? 1.5 ? tmr_0, tmr_1 timer clock pulse width both edges t tmcwl 2.5 ? 2.5 ? t cyc figure 25.8 sci asynchronous t scyc 4 ? 4 ? t cyc figure 25.9 input clock cycle synchronous 6 ? 6 ? input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 ? 1.5 t cyc input clock fall time t sckf ? 1.5 ? 1.5 transmit data delay time t txd ? 75 ? 50 ns figure 25.10 receive data setup time (synchronous) t rxs 75 ? 50 ? ns receive data hold time (synchronous) t rxh 75 ? 50 ? ns
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 635 of 656 rej09b0071-0500 table 25.21 i 2 c bus timing conditions: v cc = 2.7 v to 5.5 v, v ss = 0 v, = 5 mhz to maximum operating frequency, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit test conditions remarks scl input cycle time t scl 12 t cyc ? ? ns scl input high pulse width t sclh 3 t cyc ? ? ns scl input low pulse width t scll 5 t cyc ? ? ns scl, sda input rise time t sr ? ? 7.5 t cyc * ns scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse elimination time t sp ? ? 1 t cyc ns sda input bus free time t buf 5 t cyc ? ? ns start condition input hold time t stah 3 t cyc ? ? ns retransmission start condition input setup time t stas 3 t cyc ? ? ns stop condition input setup time t stos 3 t cyc ? ? ns data input setup time t sdas 0.5 t cyc ? ? ns data input hold time t sdah 0 ? ? ns figure 25.11 scl, sda load capacitance c b ? ? 400 pf note: * t sr can be set to 7.5 t cyc or 17.5 t cyc according to the clock used for the i 2 c module. for details, see section 14.5, usage notes.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 636 of 656 rej09b0071-0500 25.3.4 a/d conversion characteristics table 25.22 lists the a/d conversion characteristics. table 25.22 a/d conversion characteristics condition b (masked-rom version): v cc = 2.7 v to 5.5 v * , av cc = 2.7 v to 5.5 v * , v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 to 13.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition d (masked-rom version): v cc = 4.0 v to 5.5 v * , av cc = 4.0 v to 5.5 v * , v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition b condition d 13.5 mhz 20.5 mhz item min. typ. max. min. typ. max. unit resolution 10 10 10 10 10 10 bits conversion time 9.6 ? ? 6.3 ? ? s analog input capacitance ? ? 20 ? ? 20 pf permissible signal-source impedance ? ? 5 ? ? 5 k nonlinearity error ? ? 6.0 ? ? 3.0 lsb offset error ? ? 4.0 ? ? 2.0 lsb full-scale error ? ? 4.0 ? ? 2.0 lsb quantization error ? ? 0.5 ? ? 0.5 lsb absolute accuracy ? ? 8.0 ? ? 4.0 lsb note: * an0 and an1 can be used only when vcc = avcc.
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 637 of 656 rej09b0071-0500 25.3.5 lcd characteristics table 25.23 lists the lcd characteristics. table 25.23 lcd characteristics condition b (masked-rom version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 2 to 13.5 mhz, t a = ?20c to +75c condition d (masked-rom version): v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ref = 4.0 v to av cc , v ss = av ss = 0 v, = 32.768 khz, 10 to 20.5 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wid e-range specifications) condition b condition d standard value standard value item symbol applicable pins test conditions min. typ. max. min. typ. max. unit notes segment driver step-down voltage v ds seg1 to seg40 id = 2 a ? ? 0.6 ? ? 0.6 v * 1 common driver step-down voltage v dc com1 to com4 id = 2 a ? ? 0.3 ? ? 0.3 v * 1 lcd power supply division resistor r lcd between v1 and v ss 150 360 800 150 360 800 k lcd voltage v lcd v1 3.0 ? v cc 4.0 ? v cc v * 2 notes: 1. voltage step-down between power supply pins v1, v2, v3, and vss and segment pins. 2. if the lcd voltage is provided by an external power supply, the following relationship must be maintained: v cc v1 v2 v3 v ss .
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 638 of 656 rej09b0071-0500 25.4 operation timing operation timings are shown below. 25.4.1 oscillator settling timing figure 25.4 shows the oscillator settling timing. t osc1 t dext extal vcc internal clock stby res t dext t osc1 figure 25.4 oscillator settling timing 25.4.2 control signal timings control signal timings are shown below. ? reset input timing figure 25.5 shows the reset input timing. ? interrupt input timing figure 25.6 shows the nmi, irq interrupt reset input timing. t resw res figure 25.5 reset input timing
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 639 of 656 rej09b0071-0500 nmi irq t nmiw t irqw figure 25.6 interrupt input timing 25.4.3 timing of on-chip peripheral modules figures 25.7 to 25.12 show timing of on-chip peripheral modules. tclka to tclkc, tclkd * note: * supported only by the h8s/2268 group. t tckwh t tckwl figure 25.7 tpu clock input timing tmci01, tmci23 * , tmci4 * t tmcwh t tmcwl note: * supported only by the h8s/2268 group. figure 25.8 8-bit timer clock input timing sck0 to sck2 t sckw t sckr t sckf t scyc figure 25.9 sck clock input timing
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 640 of 656 rej09b0071-0500 txd0 to txd2 (transmit data) rxd0 to rxd2 (receive data) sck0 to sck2 t rxs t rxh t txd figure 25.10 sci input/output timing (clock synchronous mode) t buf t stah t stas t sp t stos t sclh t scll t sf t sr t scl t sdah t sdas p * 1 s * 1 s r * 1 v ih v il sda0 to sda1 * 2 scl0 to scl1 * 2 s, p, and sr indicate the following conditions. s : start condition p : stop condition sr : retransmission start condition supported only by the h8s/2268 group. 1. 2. notes: figure 25.11 i 2 c bus interface input/output timing (option)
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 641 of 656 rej09b0071-0500 toned gnd r l = 100 k figure 25.12 toned load circuit (supported only by the h8s/2268 group) 25.5 usage note the f-ztat and masked rom versions both satisfy the electrical character istics shown in this manual, but actual electrical characteristic values , operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, and so on. when system evaluation testing is carried out using the f-ztat version, the same evaluation testing should also be conducted for the masked rom version when changing over to that version. when combination of the f-ztat version of the h8s/2268 group and the masked rom version of the h8s/2264 group is used, the fo llowing condition should be satisfied. ? stabilization capacitance between the cvcc pin and ground = 0.2 f ? vcc = avcc
section 25 electrical characteristics rev. 5.00 sep. 01, 2009 page 642 of 656 rej09b0071-0500
appendix a i/o port states in each pin state rev. 5.00 sep. 01, 2009 page 643 of 656 rej09b0071-0500 appendix a i/o port states in each pin state a.1 i/o port state in each pin state of h8s/2268 group port name reset hardware standby mode software standby mode watch mode program execution state sleep mode subsleep mode port 1 t t keep keep i/o port port 3 t t keep keep i/o port port 4 t t t t i/o port port 7 t t keep keep i/o port p97/da1 p96/da0 t t [daoen = 1] keep [daoen = 0] t [daoen = 1] keep [daoen = 0] t input port port f t t keep keep i/o port ph7 t t t t input port ph3 to ph0 t t [common output] port [otherwise] keep [common output] com4 to com1 [otherwise] keep [common output] com4 to com1 [otherwise] i/o port port j t t [segment output] port [otherwise] keep [segment output] seg8 to seg1 [otherwise] keep [segment output] seg8 to seg1 [otherwise] i/o port port k t t [segment output] port [otherwise] keep [segment output] seg16 to seg9 [otherwise] keep [segment output] seg16 to seg9 [otherwise] i/o port port l t t [segment output] port [otherwise] keep [segment output] seg24 to seg17 [otherwise] keep [segment output] seg24 to seg17 [otherwise] i/o port
appendix a i/o port states in each pin state rev. 5.00 sep. 01, 2009 page 644 of 656 rej09b0071-0500 port name reset hardware standby mode software standby mode watch mode program execution state sleep mode subsleep mode port m t t [segment output] port [otherwise] keep [segment output] seg32 to seg25 [otherwise] keep [segment output] seg32 to seg25 [otherwise] i/o port port n t t [segment output] port [otherwise] keep [segment output] seg40 to seg33 [otherwise] keep [segment output] seg40 to seg33 [otherwise] i/o port a.2 i/o port state in each pin state of h8s/2264 group port name reset hardware standby mode software standby mode watch mode program execution state sleep mode subsleep mode port 1 t t keep keep i/o port port 3 t t keep keep i/o port port 4 t t t t input port port 7 t t keep keep i/o port port 9 t t t t input port port f t t keep keep i/o port ph7 t t t t input port ph3 to ph0 t t [common output] port [otherwise] keep [common output] com4 to com1 [otherwise] keep [common output] com4 to com1 [otherwise] i/o port port j t t [segment output] port [otherwise] keep [segment output] seg8 to seg1 [otherwise] keep [segment output] seg8 to seg1 [otherwise] i/o port
appendix a i/o port states in each pin state rev. 5.00 sep. 01, 2009 page 645 of 656 rej09b0071-0500 port name reset hardware standby mode software standby mode watch mode program execution state sleep mode subsleep mode port k t t [segment output] port [otherwise] keep [segment output] seg16 to seg9 [otherwise] keep [segment output] seg16 to seg9 [otherwise] i/o port port l t t [segment output] port [otherwise] keep [segment output] seg24 to seg17 [otherwise] keep [segment output] seg24 to seg17 [otherwise] i/o port seg40 to seg25 t t t [segment output] seg40 to seg25 [otherwise] t [segment output] seg40 to seg25 [otherwise] t legend: h: high level t: high-impedance keep: input port becomes high-impedance, output port retains state port: determined by port setting (input is high-impedance)
appendix b product codes rev. 5.00 sep. 01, 2009 page 646 of 656 rej09b0071-0500 appendix b product codes ? h8s/2268 group product type product code mark code package (renesas package code) operating voltage hd64f2268te13 100-pin tqfp (tfp-100b, tfp-100bv) hd64f2268tf13 100-pin tqfp (tfp-100g, tfp-100gv) hd64f2268fa13 100-pin qfp (fp-100b, fp-100bv) 3.0 v to 5.5 v hd64f2268te20 100-pin tqfp (tfp-100b, tfp-100bv) hd64f2268tf20 100-pin tqfp (tfp-100g, tfp-100gv) h8s/2268 f-ztat version standard product hd64f2268 hd64f2268fa20 100-pin qfp (fp-100b, fp-100bv) 4.0 v to 5.5 v hd64f2266te13 100-pin tqfp (tfp-100b, tfp-100bv) hd64f2266tf13 100-pin tqfp (tfp-100g, tfp-100gv) hd64f2266fa13 100-pin qfp (fp-100b, fp-100bv) 3.0 v to 5.5 v hd64f2266te20 100-pin tqfp (tfp-100b, tfp-100bv) h8s/2266 f-ztat version standard product hd64f2266 hd64f2266tf20 100-pin tqfp (tfp-100g, tfp-100gv) 4.0 v to 5.5 v hd64f2266fa20 100-pin qfp (fp-100b, fp-100bv)
appendix b product codes rev. 5.00 sep. 01, 2009 page 647 of 656 rej09b0071-0500 product type product code mark code package (renesas package code) operating voltage hd64f2265te13 100-pin tqfp (tfp-100b, tfp-100bv) hd64f2265tf13 100-pin tqfp (tfp-100g, tfp-100gv) hd64f2265fa13 100-pin qfp (fp-100b, fp-100bv) 3.0 v to 5.5 v hd64f2265te20 100-pin tqfp (tfp-100b, tfp-100bv) h8s/2265 f-ztat version standard product hd64f2265 hd64f2265tf20 100-pin tqfp (tfp-100g, tfp-100gv) 4.0 v to 5.5 v hd64f2265fa20 100-pin qfp (fp-100b, fp-100bv)
appendix b product codes rev. 5.00 sep. 01, 2009 page 648 of 656 rej09b0071-0500 ? h8s/2264 group product type product code mark code package (renesas package code) operating voltage hd6432264 hd6432264(a ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 2.7 v to 5.5 v h8s/2264 masked- rom version standard product hd6432264(a ** )fa 100-pin qfp (fp-100b, fp-100bv) hd6432264(f ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 4.0 v to 5.5 v hd6432264(f ** )fa 100-pin qfp (fp-100b, fp-100bv) hd6432264w hd6432264w(a ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 2.7 v to 5.5 v version with on-chip i 2 c bus interface hd6432264w(a ** )fa 100-pin qfp (fp-100b, fp-100bv) hd6432264w(f ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 4.0 v to 5.5 v hd6432264w(f ** )fa 100-pin qfp (fp-100b, fp-100bv) h8s/2262 standard product hd6432262 hd6432262(a ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 2.7 v to 5.5 v masked- rom version hd6432262(a ** )fa 100-pin qfp (fp-100b, fp-100bv) hd6432262(f ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 4.0 v to 5.5 v hd6432262(f ** )fa 100-pin qfp (fp-100b, fp-100bv)
appendix b product codes rev. 5.00 sep. 01, 2009 page 649 of 656 rej09b0071-0500 product type product code mark code package (renesas package code) operating voltage h8s/2262 hd6432262w hd6432262w(a ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 2.7 v to 5.5 v masked- rom version version with on-chip i 2 c bus interface hd6432262w(a ** )fa 100-pin qfp (fp-100b, fp-100bv) hd6432262w(f ** )tf 100-pin tqfp (tfp-100g, tfp-100gv) 4.0 v to 5.5 v hd6432262w(f ** )fa 100-pin qfp (fp-100b, fp-100bv) legend: (a ** ), (f ** ): rom code note: some products above are in the developing or planning stage. please contact renesas agency to confirm the present state of each product.
appendix c package dimensions rev. 5.00 sep. 01, 2009 page 650 of 656 rej09b0071-0500 appendix c package dimensions the package dimensions that are shown in the renesas semiconductor packages data book have priority. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. ptqp0100ka-a p-tqfp100-14x14-0.50 1.00 1.00 0.08 0.10 0.5 8 0 15.8 16.0 16.2 0.15 0.20 1.20 0.20 0.10 0.00 0.27 0.22 0.17 0.22 0.17 0.12 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e e l h mass[typ.] 0.5g tfp-100b/tfp-100bv renesas code jeita package code previous code 0.6 0.5 0.4 max nom min dimension in millimeters symbol reference 14 1.00 16.2 16.0 15.8 1.0 14 index mark * 1 * 2 * 3 p e d e d 100 1 f xm y 26 25 76 75 50 51 z z h e h d b 2 1 1 detail f c l a a a l terminal cross section p 1 1 b c b c figure c.1 tfp-100b and tfp-100bv package dimensions (h8s/2268 group only)
appendix c package dimensions rev. 5.00 sep. 01, 2009 page 651 of 656 rej09b0071-0500 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. index mark * 1 * 2 * 3 p e d e d yx f 100 125 26 76 75 50 51 e h d h b z z 2 1 1 detail f c a a l a l terminal cross section 1 1 p b c c b ptqp0100lc-a p-tqfp100-12x12-0.40 h l e e c a d e a h a b b c x y z z l 2 d e 1 p 1 1 d e 1 mass[typ.] 0.4g reference symbol dimension in millimeters min nom max previous code jeita package code renesas code tfp-100g/tfp-100gv 1.0 0.10 0 8 0.4 0.12 0.17 0.22 0.13 0.18 0.23 0.00 0.10 0.20 1.20 13.8 14.0 14.2 1.00 12 0.16 0.15 0.4 0.5 0.6 0.07 14.2 14.0 13.8 1.2 12 1.2 m figure c.2 tfp-100g and tfp-100gv package dimensions
appendix c package dimensions rev. 5.00 sep. 01, 2009 page 652 of 656 rej09b0071-0500 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. * 1 * 2 * 3 p e d e d f 100 12 5 26 76 75 51 50 xm y z z d h e h b terminal cross section p 1 1 c b c b 2 1 1 detail f c a a l l a prqp0100ka-a p-qfp100-14x14-0.50 1.0 1.0 0.08 0.10 0.5 8 0 0.25 0.12 0.15 0.20 0.00 0.27 0.22 0.17 0.22 0.17 0.12 3.05 16.3 16.0 15.7 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e e l h mass[typ.] 1.2g fp-100b/fp-100bv renesas code jeita package code previous code 0.7 0.5 0.3 max nom min dimension in millimeters symbol reference 14 2.70 16.3 16.0 15.7 1.0 14 figure c.3 fp-100b and fp-100bv package dimensions
index rev. 5.00 sep. 01, 2009 page 653 of 656 rej09b0071-0500 index 16-bit timer pulse unit (tpu).................. 185 buffer operation.................................. 225 buffer operation timing ...................... 243 counter ope ration ............................... 218 free-running count operation.............. 219 input capture function......................... 221 input capture signal timing ................. 241 output compare output timing............ 240 periodic count operation ..................... 219 phase counti ng mode .......................... 233 pwm modes ....................................... 228 synchronous operation ....................... 223 tcnt count timing............................. 240 toggle ou tput...................................... 220 waveform output by compare match.. 220 8-bit reload timer .................................... 280 automatic reload timer operation ....... 285 interval timer operation ...................... 284 8-bit timers.............................................. 257 16-bit count mode ............................... 273 cascaded connection........................... 273 compare-match count mode............... 273 pulse output ........................................ 268 tcnt incrementation timing.............. 269 toggle ou tput...................................... 277 a/d converter ......................................... 443 a/d converter activation..................... 239 analog input channel .......................... 446 conversion time.................................. 454 external trigger ................................... 456 scan mode........................................... 453 single m ode ........................................ 451 address map ............................................. 57 address space ........................................... 20 addressing modes..................................... 40 absolute address................................... 42 immediate .............................................43 memory indirect....................................43 program-counter relative.......................43 register direct .......................................41 register indirect ....................................41 register indirect w ith displacement ......41 register indirect with post-increment ...42 register indirect with pre-decrement ....42 bcc ............................................................37 break address ..........................................103 break condition.......................................105 bus arbitration.........................................113 bus cycle.................................................111 bus masters .............................................113 clock pulse ge nerator..............................539 condition field ..........................................39 condition-code register.............................24 d/a converter..........................................463 data direction register (ddr).................139 data register (dr)...................................139 data transfer controller ...........................115 activated by software .........................132 block transfer mode ............................129 chain transfer......................................131 dtc vector table.................................123 normal mode ......................................127 register information ...........................123 repeat mode........................................128 software activation ..................... 132, 136 vector number for the software activation interrupt...............................................121 dtmf generation circuit ........................493 effective address ................................. 40, 44 effective address extension.......................39
index rev. 5.00 sep. 01, 2009 page 654 of 656 rej09b0071-0500 exception handling ................................... 59 interrupts............................................... 63 reset exception handling ...................... 61 stack status ........................................... 65 traces.................................................... 63 trap instruction..................................... 64 exception vector table ............................ 60 extended control register .......................... 23 flash memory ......................................... 503 boot m ode........................................... 518 emulation............................................ 522 erase/erase-verify ............................... 527 erasing units ....................................... 508 error prot ection................................... 529 hardware protection ........................... 529 program/program-verify ..................... 525 software protection............................. 529 user program mode ............................ 521 general register......................................... 26 i 2 c bus interface...................................... 383 i 2 c bus format ..................................... 406 noise cancelers ................................... 427 serial format ....................................... 406 input pull-up mos function ................... 139 instruction set ........................................... 29 arithmetic operations instructions........ 32 bit manipulation instructions ............... 35 block data transfer instructions ............ 39 branch instructions ............................... 37 data transfer instructions ...................... 31 logic operations instructions................ 34 shift instructions................................... 34 system control instructions................... 38 interrupt adi ..................................................... 456 cmia.................................................. 274 cmib .................................................. 274 eri ......................................................375 nmi.....................................................299 ovi .....................................................274 rxi......................................................375 swdtend .........................................132 tci ......................................................238 tei ......................................................375 tgi......................................................238 txi......................................................375 wovi..................................................299 interrupt control modes.............................88 interrupt controller ....................................67 interrupt exception handling vector table..84 interrupt mask bit......................................24 lcd controller/driver .............................469 common driv ers..................................473 duty cycle ...........................................469 lcd display ........................................482 lcd ram ..........................................483 segment driver ....................................475 memory cycle .........................................111 on-board pr ogramming...........................518 operating mode selection..........................55 operation field ..........................................39 pc break controller .................................103 power-down modes.................................551 direct transitions .................................569 hardware standby mode......................564 medium-speed mode...........................560 module stop mode...............................565 sleep mode..........................................561 software standby mode.......................562 sub-active mode..................................568 sub-sleep mode...................................567 watch m ode ........................................566 program counter........................................23
index rev. 5.00 sep. 01, 2009 page 655 of 656 rej09b0071-0500 program/erase protection ........................ 529 programmer mode .................................. 530 register adcr ......................... 449, 580, 589, 596 adcsr ....................... 447, 580, 589, 596 addr ......................... 446, 580, 588, 595 bara ......................... 104, 576, 584, 592 barb ......................... 105, 576, 585, 592 bcra ......................... 105, 576, 585, 592 bcrb.......................... 106, 577, 585, 592 brr ............................ 326, 579, 588, 595 cra ............................ 119, 574, 582, 590 crb ............................ 119, 574, 582, 590 dacr ......................... 465, 575, 583, 591 dadr ......................... 464, 575, 583, 591 dar............................ 119, 574, 582, 590 ddcswr ................... 405, 575, 583, 591 dtcer ....................... 120, 577, 585, 592 dtcr.......................... 495, 574, 582, 590 dtlr.......................... 496, 574, 582, 590 dtvecr .................... 121, 577, 585, 592 ebr1 .......................... 514, 580, 589, 596 ebr2 .......................... 515, 581, 589, 596 flmcr1..................... 512, 580, 589, 596 flmcr2..................... 513, 580, 589, 596 flpwcr .................... 516, 581, 589, 596 iccr........................... 395, 579, 588, 595 icdr........................... 388, 579, 588, 595 icmr .......................... 391, 579, 588, 595 icsr ........................... 401, 579, 588, 595 ienr1........................... 80, 575, 583, 591 ier................................ 74, 5 77, 585, 592 ipr ................................ 73, 5 77, 585, 593 iscr ............................. 75, 5 77, 585, 592 isr ................................ 77, 5 77, 585, 592 iwpr ............................ 80, 5 75, 583, 591 lcd ram .................. 483, 574, 582, 590 lcr ............................ 476, 574, 582, 590 lcr2 .......................... 478, 574, 582, 590 lpcr........................... 472, 574, 582, 590 lpwrcr .................... 541, 576, 584, 592 mdcr........................... 56, 576, 584, 592 mra ........................... 117, 574, 582, 590 mrb............................ 118, 574, 582, 590 mstpcr..................... 558, 584, 590, 592 p1ddr........................ 145, 577, 585, 592 p1dr........................... 146, 578, 586, 593 p3ddr........................ 151, 577, 585, 592 p3dr........................... 152, 578, 586, 593 p3odr........................ 153, 577, 585, 593 p7ddr........................ 158, 577, 585, 592 p7dr........................... 158, 578, 586, 593 pfddr........................ 163, 577, 585, 593 pfdr........................... 163, 578, 586, 593 phddr ....................... 165, 575, 583, 590 phdr.......................... 166, 575, 583, 591 pjddr ........................ 170, 575, 583, 590 pjdr ........................... 170, 575, 583, 591 pjpcr ......................... 171, 575, 583, 591 pkddr ....................... 174, 575, 583, 590 pkdr.......................... 174, 575, 583, 591 plddr ....................... 176, 575, 583, 590 pldr .......................... 177, 575, 583, 591 pmddr ...................... 178, 575, 583, 590 pmdr ......................... 179, 575, 583, 591 pnddr ....................... 181, 575, 583, 591 pndr.......................... 182, 575, 583, 591 port1 ........................ 146, 581, 589, 596 port3 ........................ 153, 581, 589, 596 port4 ........................ 157, 581, 589, 596 port7 ........................ 159, 581, 589, 596 port9 ........................ 162, 581, 589, 596 portf ........................ 164, 581, 589, 596 porth ....................... 166, 575, 583, 591 portj......................... 171, 575, 583, 591 portk ....................... 175, 575, 583, 591 portl........................ 177, 575, 583, 591 portm....................... 180, 575, 583, 591 portn ....................... 182, 575, 583, 591
index rev. 5.00 sep. 01, 2009 page 656 of 656 rej09b0071-0500 ramer ...................... 515, 577, 586, 593 rdr ............................ 308, 579, 588, 595 rsr..................................................... 308 rstcsr ..................... 295, 579, 587, 594 sar ............................ 119, 574, 582, 590 sarx.................. 390, 579, 580, 588, 595 sbycr ....................... 556, 576, 584, 592 sckcr ....................... 540, 576, 584, 592 scmr ......................... 325, 579, 588, 595 scr............................. 313, 579, 588, 595 scrx.......................... 394, 575, 583, 591 semr ......................... 334, 576, 584, 592 smr............................ 309, 579, 587, 595 ssr ............................. 318, 579, 588, 595 syscr.......................... 71, 5 76, 584, 592 tcnt..........213, 291, 578, 579, 586, 587, .................................................... 593, 594 tcora....................... 260, 579, 587, 594 tcorb ....................... 260, 579, 587, 594 tcr ............192, 261, 578, 579, 586, 587, .................................................... 593, 594 tcsr .......................... 263, 579, 587, 594 tdr ............................ 308, 579, 588, 595 tgr ............................ 213, 578, 586, 593 tier ........................... 207, 578, 586, 593 tior........................... 197, 578, 586, 593 tmdr......................... 195, 578, 586, 593 tsr ............................. 209, 578, 586, 593 tstr........................... 214, 577, 585, 593 tsyr .......................... 215, 577, 585, 593 wpcr ......................... 172, 575, 583, 591 register field.............................................39 reset..........................................................61 serial communication interface (sci).....303 asynchronous mode............................338 bit rate.................................................326 break ...................................................376 clocked synchr onous m ode ................355 framing error ......................................345 mark state............................................376 multiprocessor communication function ...............................................349 overrun error.......................................345 parity error ..........................................345 smart card ...............................................303 smart card interface ................................363 stack pointer .............................................22 watchdog timer.......................................289 interval timer mode.............................297 overflow .............................................298 watchdog timer mode.........................296
renesas 16-bit single- chip microcomputer hardware manual h8s/2268 group, h8s/2264 group publication date: 1st edition, april 2001 rev.5.00, september 1, 2009 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ?2009. renesas technology corp., all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.2

h8s/2268 group, h8s/2264 group rej09b0071-0500 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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